寬頻高線性度封包追蹤前端模組設計

Abstract

本論文提出一寬頻且支援WCDMA、LTE、WLAN之0.18 μm SiGe BiCMOS 功率放大器(Power Amplifier ; PA)。此PA於單晶片中整合了可調式輸入匹配網路、寬頻輸出匹配網路與可調式偏壓電路來使得在不同調變訊號及操作頻率下皆可達成高線性度與高功率之輸出表現。所提出之PA使用三級差動式架構而成，在不使用任何貫穿基板結構(TSV)的技術下可以達成41.3-42 dB的增益、28.2-28.6 dBm的1dB壓縮點輸出功率，並得到20.8-27.6 % 的功率附加效率(Power Added Efficiency ; PAE)於1.85-2.5 GHz的操作頻率下。為了進一步驗證所提出之PA的功用，本論文亦設計封包追蹤放大器來結合PA，於2.35GHz 16QAM LTE 20-MHz 頻寬下，可達24.7dBm之線性輸出功率，並同時符合-33dBc 之線性度規範，且再提升PAE 6.5%。 封包追蹤前端模組由封包追蹤電源調變器(Envelope Tracking Supply Modulator ; ETSM)、雙功率模態功率放大器、單刀雙擲開關電路所組成，並應用於LTE-A 頻帶內載波聚合技術。ETSM使用雙交錯路徑電流重複利用結構來獲得較高的頻寬與效率。量測效率於頻寬分別為1 × 20MHz、2 × 20MHz 、3 × 20MHz、4 × 20MHz之16-QAM LTE-A 載波聚合訊號下，可分別達到79.6%、76.4%、74%與72.8%之效率，而此時之峰值頻均功率比(Peak to Average Power Ratio ; PAPR)分別為7.4 dB、9.6 dB、11.2 dB與12.3 dB。雙功率模態SiGe BiCMOS PA被實現來結合ETSM以改善鄰近功率洩漏比(Adjacent Channel Leakage Ratio ; ACLR)與向量誤差比(Error Vector Magnitude ; EVM)。於操作頻率1.95GHz，1 × 20MHz、2 × 20MHz 、3 × 20MHz調變頻寬下，輸出功率為26.8 dBm、24.3 dBm、21.7 dBm時，ACLR可改善11.7 dB、7.9 dB和4.7 dB而EVM可改善7.1 %、6.1 %與4.1 %。單刀雙擲開關結合ETSM可降低0.3 dB功率損耗，並獲得1.1-dB的ACLR改善與0.7 %的EVM改善，於12 dBm輸入功率下。封包追蹤前端模組操作於12.5 dB PAPR 64 QAM 4 × 20 MHz 頻寬之LTE-A載波聚合訊號下，於輸出功率13.1 dBm時，可獲得1.3 dB的ACLR改善與1 %的EVM改善以達成寬頻高線性度之射頻前端模組應用。 此論文同時也提出了集極電壓變化技術來改善PA之線性度。PA之三階交互調變行為於此論文中將被分析並透過集極電壓調變來改善交互調變失真之非線性程度。此集極電壓調變技術改善非線性之方法將於此論文中被透過實驗與理論來進行驗證。經由SiGe BiCMOS PA實驗結果顯示，透過集極電壓調變可以比傳統固定供給電壓之PA提升約2.3 dB之線性輸出功率。

A power amplifier supporting wideband code division multiple access (WCDMA), long-term evolution (LTE) and wireless local area network (WLAN) applications has been implemented in 0.18 SiGe BiCMOS technology. The power amplifier integrates a tunable input matching network, a broadband output matching network, and adaptive bias circuits in a single chip to achieve high linearity and high power in different modulation schemes and operating bands. The three-stage power amplifier adopts differential-type configuration without using through-silicon-via technology to deliver 41.3-42 dB of gain and 28.2-28.6 dBm of 1-dB compression output power with a 20.8-27.6% power-added efficiency at 1.85-2.5 GHz. To further validate the usefulness of the proposed power amplifier, the envelope tracking power amplifier is designed to improve the power-added efficiency by 6.5% within the linearity specification of a 24.7 dBm average output power and a -33 dBc adjacent channel leakage ratio for 2.35 GHz 16QAM time-division LTE signal with 20 MHz bandwidth. The envelope-tracking frontend module (ETFEM) consisting of an envelope-tracking supply modulator (ETSM), a dual-power-mode power amplifier, and a single-pole-double-throw (SPDT) switch is proposed for the long term evolution-advanced (LTE-A) intra-band carrier aggregation (CA) signal. The linear stage of ETSM is implemented by introducing the dual-path crossover current-reuse mechanism to obtain the measured efficiency 79.6 %, 76.4 %, 74 %, and 72.8 % for the 7.4-dB, 9.6-dB, 11.2-dB, and 12.3-dB PAPR 16-QAM LTE-A CA signals with 1 20-MHz, 2 20-MHz, 3 20-MHz, and 4 20-MHz bandwidths, respectively. A SiGe BiCMOS dual-power-mode power amplifier with two output power modes is realized and incorporated with ETSM to improve the adjacent channel leakage ratio (ACLR) by 11.7 dB, 7.9 dB, and 4.7 dB and the error vector magnitude (EVM) by 7.1 %, 6.1 %, and 4.1 % at the 26.8-dBm, 24.3-dBm, and 21.7-dBm output powers for the LTE-A 16-QAM signals with 1 20-MHz, 2 20-MHz, and 3 20-MHz bandwidths at 1.95 GHz, respectively. The SPDT switch integrated with ETSM provides the 0.3-dB power loss reduction, the 1.1-dB ACLR improvement, and the 0.7-% EVM enhancement at the 12-dBm average input power. The ETFEM operated at the 12.5-dB PAPR 64-QAM LTE-A CA signal with 4 20-MHz bandwidth demonstrates that the improvements of 1.3-dB ACLR and 1-% EVM at the 13.1-dBm output power are achieved for the wide-bandwidth and high-linearity FEM applications. This thesis also proposes a power amplifier with the various collector voltages technique to linearize the power amplifier. The third-order intermodulation term in the behavior model of the power transistor is analyzed to demonstrate the minimum third-order intermodulation distortion for the power amplifier with the various collector voltages technique. This various collector voltages technique for reducing the third-order intermodulation distortion of the power amplifier is experimentally and theoretically verified. A SiGe BiCMOS power amplifier with the various collector voltages technique is designed and implemented. Results demonstrate that the linear output power of the proposed power amplifier is 2.3 dB higher than the power amplifier with the fixed supply voltage.