4H-SiC金氧半場效電晶體及接面位障蕭基二極體設計與製作

Abstract

本論文利用模擬軟體TCAD Sentaurus設計4H-SiC金氧半場效電晶體，先探討傳統平面式閘極的結構，優化其JFET寬度、漂移區濃度、閘極氧化層厚度。接著為了降低特徵導通電阻，同時維持高崩潰電壓，採用溝槽填充的技術，製作出超級接面結構的金氧半場效電晶體，又這項技術目前全世界僅有少數先進國家擁有。其製程流程是先蝕刻出溝槽，再回填P型半導體，形成超級接面結構，並且討論電荷平衡對於電性的影響，最終經過最佳化設計的超級接面平面式閘極金氧半場效電晶體達到臨界電壓2.23伏特、特徵導通電阻1.48mΩ·cm^2、崩潰電壓743伏特。相較由日本的國家先進工業科學技術研究所(National Institute of Advanced Industrial Science and Technology, AIST)所設計的金氧半場效電晶體，同樣以4H-SiC晶圓製作、平面式閘極、目前全世界最低的特徵導通電阻，其臨界電壓2.0-2.7伏特、特徵導通電阻1.8mΩ·cm^2、崩潰電壓660伏特，而本論文設計的超級接面金氧半場效電晶體的特徵導通電阻降低了17%、崩潰電壓提高了12%。 接著針對接面位障蕭基二極體(Junction barrier Schottky diode, JBS)進行研究，其順向偏壓有著類似蕭基二極體的低導通電壓、快速切換特性，且逆向偏壓類似PiN二極體的特性，利用PN接面形成的空乏區夾住漏電流通道。先以模擬軟體調整P型離子佈值劑量，再模擬其電性，接著將模擬得到的劑量進行製程實驗，並且設計不同的主動區P+離子佈值開口的排列方式，相較於傳統的長條型P+離子佈值開口的蕭基接面比例更高，故順向偏壓時，達到低導通電壓，且逆向偏壓時也達到低漏電流、高崩潰電壓的目標。

In this paper, I use the simulation software TCAD sentaurus to design the 4H-SiC metal oxide semiconductor field effect transistor (MOSFET). First, the traditional planar gate MOSFET is discussed, and its JFET width, drift region concentration and gate oxide thickness are optimized. Then, in order to reduce the specific on-resistance (Ron,sp) while maintaining a high breakdown voltage, I take trench-refilling method to fabricate super junction MOSFET. This technology is currently owned by only a few countries. The process flow is to etch the trench, then refill the P-type semiconductor to form the super junction structure, and study the impact of charge balance on the electrical properties. Finally, the super junction planar gate MOSFET is optimized. The design of super junction MOSFET reaches the threshold voltage 2.23 volts, specific on-resistance of 1.48 mΩ · cm2, and breakdown voltage of 743 volts. Compared with the MOSFET designed by National Institute of Advanced Industrial Science and Technology (AIST) , it is also made of 4H-SiC wafers, planar gate , and The world's lowest specific on-resistance has a critical voltage of 2.0 - 2.7 volts, specific on-resistance of 1.8 mΩ · cm2 , and breakdown voltage of 660 volts. The specific on-resistance of the super junction MOSFET designed in this paper has been reduced by 17%, and the breakdown voltage has been increased by 12%. Next, the Junction barrier Schottky diode (JBS) is studied. Its forward bias has low voltage drop and fast switching characteristics similar to the Schottky diode, PN junction is used to clamp the leakage current when it is at reverse bias, and the reverse bias characteristics is similar to PiN diode. I use TCAD sentaurus to adjust the P-type implantation dose, and then simulate its electrical properties. Then, the simulated dose is applied to experiment. I design different arrangements of P+ implantation window in the active area, which have more Schottky area than stripe shape. The more Schottky area, the lower voltage drop. Besides, different arrangements of P+ implantation window cause low leakage current and high breakdown voltage when reverse bias.