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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李坤彥 | zh_TW |
| dc.contributor.advisor | Kung-Yen Lee | en |
| dc.contributor.author | 洪振閔 | zh_TW |
| dc.contributor.author | Jhen-Min Hong | en |
| dc.date.accessioned | 2021-07-10T21:48:48Z | - |
| dc.date.available | 2024-12-11 | - |
| dc.date.copyright | 2019-12-17 | - |
| dc.date.issued | 2019 | - |
| dc.date.submitted | 2002-01-01 | - |
| dc.identifier.citation | [1] Lee, H. S. (2005). High power bipolar junction transistors in silicon carbide (Doctoral dissertation, KTH).
[2] Mastro, M. A., Kuramata, A., Calkins, J., Kim, J., Ren, F., & Pearton, S. J. (2017). Perspective—opportunities and future directions for Ga2O3. ECS Journal of Solid State Science and Technology, 6(5), P356-P359. [3] Baliga, B. J. (2010). Fundamentals of power semiconductor devices. Springer Science & Business Media. [4] Shenoy, P. M., Bhalla, A., & Dolny, G. M. (1999, May). Analysis of the effect of charge imbalance on the static and dynamic characteristics of the super junction MOSFET. In 11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No. 99CH36312) (pp. 99-102). IEEE. [5] Sung, W., & Baliga, B. J. (2017). A comparative study 4500-V edge termination techniques for SiC devices. IEEE Transactions on Electron Devices, 64(4), 1647-1652. [6] Bolotnikov, A., Losee, P. A., Deeb, P., Wang, M. L., Dunne, G., Kretchmer, J., ... & Stevanovic, L. (2016). Design of area-efficient, robust and reliable junction termination extension in SiC devices. In Materials Science Forum (Vol. 858, pp. 737-740). Trans Tech Publications. [7] Hu, C. (1996, December). Gate oxide scaling limits and projection. In International Electron Devices Meeting (pp. 319-322). [8] Sun, S. C., & Plummer, J. D. (1980). Modeling of the on-resistance of LDMOS, VDMOS, and VMOS power transistors. IEEE Transactions on Electron Devices, 27(2), 356-367. [9] Barkhordarian, V. (1996). Power MOSFET basics. Powerconversion and Intelligent Motion-English Edition, 22(6). [10] Neamen, D. A. (2003). Fundamentals of Semiconductor Physics and Devices. 半導體物理與元件, 譯者: 楊賜麟), 美商麥格羅‧ 希爾國際股份有限公司, 362. [11] Singh, P. (2004, September). Power MOSFET failure mechanisms. In INTELEC 2004. 26th Annual International Telecommunications Energy Conference (pp. 499-502). IEEE. [12] Appels, J. A., & Vaes, H. M. J. (1979, December). High voltage thin layer devices (RESURF devices). In 1979 International Electron Devices Meeting (pp. 238-241). IEEE. [13] Kosugi, R., Sakuma, Y., Kojima, K., Itoh, S., Nagata, A., Yatsuo, T., ... & Okumura, H. (2013). Development of SiC super-junction (SJ) device by deep trench-filling epitaxial growth. In Materials Science Forum (Vol. 740, pp. 785-788). Trans Tech Publications. [14] Kondekar, P. N., Parikh, C. D., & Patil, M. B. (2002, June). Analysis of breakdown voltage and on resistance of super junction power MOSFET CoolMOS/sup TM/using theory of novel voltage sustaining layer. In 2002 IEEE 33rd Annual IEEE Power Electronics Specialists Conference. Proceedings (Cat. No. 02CH37289) (Vol. 4, pp. 1769-1775). IEEE. [15] Udrea, F., Deboy, G., & Fujihira, T. (2017). Superjunction power devices, history, development, and future prospects. IEEE Transactions on Electron Devices, 64(3), 713-727. [16] Yamauchi, S., Hattori, Y., & Yamaguchi, H. (2003, April). Electrical properties of super junction pn diodes fabricated by trench filling. In ISPSD'03. 2003 IEEE 15th International Symposium on Power Semiconductor Devices and ICs, 2003. Proceedings. (pp. 207-210). IEEE. [17] Webster, J. (2002). Wiley encyclopedia of electrical and electronics engineering. Biomedical Instrumentation & Technology, 36(5). [18] Masuda, T., Saito, Y., Kumazawa, T., Hatayama, T., & Harada, S. (2018). 0.63 mΩcm2/1170 V 4H-SiC super junction V-groove trench MOSFET. IEEE IEDM Tech. Dig, 177-180. [19] Harada, S., Kobayashi, Y., Kyogoku, S., Morimoto, T., Tanaka, T., Takei, M., & Okumura, H. (2018, December). First demonstration of dynamic characteristics for SiC superjunction MOSFET realized using multi-epitaxial growth method. In 2018 IEEE International Electron Devices Meeting (IEDM) (pp. 8-2). IEEE. [20] Yu, L., & Sheng, K. (2008). Modeling and optimal device design for 4H-SiC super-junction devices. IEEE Transactions on Electron Devices, 55(8), 1961-1969. [21] Hatakeyama, T., Nishio, J., Ota, C., & Shinohe, T. (2005, September). Physical modeling and scaling properties of 4H-SiC power devices. In 2005 International Conference On Simulation of Semiconductor Processes and Devices (pp. 171-174). IEEE. [22] Ortiz-Conde, A., Sánchez, F. G., Liou, J. J., Cerdeira, A., Estrada, M., & Yue, Y. (2002). A review of recent MOSFET threshold voltage extraction methods. Microelectronics reliability, 42(4-5), 583-596. [23] Harada, S., Kato, M., Suzuki, K., Okamoto, M., Yatsuo, T., Fukuda, K., & Arai, K. (2006, December). 1.8 mΩcm 2, 10 A Power MOSFET in 4H-SiC. In 2006 International Electron Devices Meeting (pp. 1-4). IEEE. [24] Nakano, Y., Nakamura, R., Sakairi, H., Mitani, S., & Nakamura, T. (2012). 690V, 1.00 mΩcm2 4H-SiC Double-Trench MOSFETs. In Materials Science Forum (Vol. 717, pp. 1069-1072). Trans Tech Publications. [25] Saito, W., Omura, I., Aida, S., Koduki, S., Izumisawa, M., Yoshioka, H., & Ogura, T. (2004, May). A 20m cm 2 600V-class Superjunction MOSFET. In Proc. ISPSD (Vol. 2004, pp. 459-462). [26] Lee, K. Y., Liu, Y. H., Wang, S. C., & Chan, L. S. (2017). Influence of the Design of Square p+ Islands on the Characteristics of 4H-SiC JBS. IEEE Transactions on Electron Devices, 64(3), 1394-1398. [27] Mayer, J. W. (1973, December). Ion implantation in semiconductors. In 1973 International Electron Devices Meeting (pp. 3-5). IEEE. [28] Troffer, T., Schadt, M., Frank, T., Itoh, H., Pensl, G., Heindl, J., ... & Maier, M. (1997). Doping of SiC by implantation of boron and aluminum. physica status solidi (a), 162(1), 277-298. [29] Kimoto, T., Itoh, A., Matsunami, H., & Okano, T. (1997). Step bunching mechanism in chemical vapor deposition of 6H–and 4H–SiC {0001}. Journal of applied physics, 81(8), 3494-3500. [30] Negoro, Y., Katsumoto, K., Kimoto, T., & Matsunami, H. (2004). Electronic behaviors of high-dose phosphorus-ion implanted 4H–SiC (0001). Journal of Applied Physics, 96(1), 224-228. [31] Zhao, Q. T., Breuer, U., Rije, E., Lenk, S., & Mantl, S. (2005). Tuning of NiSi∕ Si Schottky barrier heights by sulfur segregation during Ni silicidation. Applied physics letters, 86(6), 062108. [32] Hatzakis, M., Canavello, B. J., & Shaw, J. M. (1980). Single-step optical lift-off process. IBM Journal of Research and Development, 24(4), 452-460. [33] Jordá, X., Tournier, D., Rebollo, J., Millan, J., & Godignon, P. (2005). Temperature impact on high-current 1.2 kV SiC Schottky rectifiers. In Materials Science Forum (Vol. 483, pp. 929-932). Trans Tech Publications. [34] Kim, S. C., Bahng, W., Kang, I. H., Joo, S. J., & Kim, N. K. (2008, May). Fabrication characteristics of 1.2 kV SiC JBS diode. In 2008 26th International Conference on Microelectronics (pp. 181-184). IEEE. [35] Pérez, R., Tournier, D., Pérez-Tomás, A., Godignon, P., Mestres, N., & Millán, J. (2005). Planar edge termination design and technology considerations for 1.7-kV 4H-SiC PiN diodes. IEEE Transactions on Electron Devices, 52(10), 2309-2316. | - |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/77157 | - |
| dc.description.abstract | 本論文利用模擬軟體TCAD Sentaurus設計4H-SiC金氧半場效電晶體，先探討傳統平面式閘極的結構，優化其JFET寬度、漂移區濃度、閘極氧化層厚度。接著為了降低特徵導通電阻，同時維持高崩潰電壓，採用溝槽填充的技術，製作出超級接面結構的金氧半場效電晶體，又這項技術目前全世界僅有少數先進國家擁有。其製程流程是先蝕刻出溝槽，再回填P型半導體，形成超級接面結構，並且討論電荷平衡對於電性的影響，最終經過最佳化設計的超級接面平面式閘極金氧半場效電晶體達到臨界電壓2.23伏特、特徵導通電阻1.48mΩ·cm^2、崩潰電壓743伏特。相較由日本的國家先進工業科學技術研究所(National Institute of Advanced Industrial Science and Technology, AIST)所設計的金氧半場效電晶體，同樣以4H-SiC晶圓製作、平面式閘極、目前全世界最低的特徵導通電阻，其臨界電壓2.0-2.7伏特、特徵導通電阻1.8mΩ·cm^2、崩潰電壓660伏特，而本論文設計的超級接面金氧半場效電晶體的特徵導通電阻降低了17%、崩潰電壓提高了12%。
接著針對接面位障蕭基二極體(Junction barrier Schottky diode, JBS)進行研究，其順向偏壓有著類似蕭基二極體的低導通電壓、快速切換特性，且逆向偏壓類似PiN二極體的特性，利用PN接面形成的空乏區夾住漏電流通道。先以模擬軟體調整P型離子佈值劑量，再模擬其電性，接著將模擬得到的劑量進行製程實驗，並且設計不同的主動區P+離子佈值開口的排列方式，相較於傳統的長條型P+離子佈值開口的蕭基接面比例更高，故順向偏壓時，達到低導通電壓，且逆向偏壓時也達到低漏電流、高崩潰電壓的目標。 | zh_TW |
| dc.description.abstract | In this paper, I use the simulation software TCAD sentaurus to design the 4H-SiC metal oxide semiconductor field effect transistor (MOSFET). First, the traditional planar gate MOSFET is discussed, and its JFET width, drift region concentration and gate oxide thickness are optimized. Then, in order to reduce the specific on-resistance (Ron,sp) while maintaining a high breakdown voltage, I take trench-refilling method to fabricate super junction MOSFET. This technology is currently owned by only a few countries. The process flow is to etch the trench, then refill the P-type semiconductor to form the super junction structure, and study the impact of charge balance on the electrical properties. Finally, the super junction planar gate MOSFET is optimized. The design of super junction MOSFET reaches the threshold voltage 2.23 volts, specific on-resistance of 1.48 mΩ · cm2, and breakdown voltage of 743 volts. Compared with the MOSFET designed by National Institute of Advanced Industrial Science and Technology (AIST) , it is also made of 4H-SiC wafers, planar gate , and The world's lowest specific on-resistance has a critical voltage of 2.0 - 2.7 volts, specific on-resistance of 1.8 mΩ · cm2 , and breakdown voltage of 660 volts. The specific on-resistance of the super junction MOSFET designed in this paper has been reduced by 17%, and the breakdown voltage has been increased by 12%.
Next, the Junction barrier Schottky diode (JBS) is studied. Its forward bias has low voltage drop and fast switching characteristics similar to the Schottky diode, PN junction is used to clamp the leakage current when it is at reverse bias, and the reverse bias characteristics is similar to PiN diode. I use TCAD sentaurus to adjust the P-type implantation dose, and then simulate its electrical properties. Then, the simulated dose is applied to experiment. I design different arrangements of P+ implantation window in the active area, which have more Schottky area than stripe shape. The more Schottky area, the lower voltage drop. Besides, different arrangements of P+ implantation window cause low leakage current and high breakdown voltage when reverse bias. | en |
| dc.description.provenance | Made available in DSpace on 2021-07-10T21:48:48Z (GMT). No. of bitstreams: 1 ntu-108-R06525082-1.pdf: 5887170 bytes, checksum: 52dc0e14b9165514d77ef050ce0f9f0b (MD5) Previous issue date: 2019 | en |
| dc.description.tableofcontents | 第一章 緒論 1
1.1前言 1 1.2碳化矽材料的性質 2 1.3研究動機 4 1.4論文架構 5 第二章 元件結構原理 7 2.1 常見功率元件分類 8 2.2蕭基二極體原理 8 2.3 PN二極體原理 14 2.4接面位障蕭基二極體 15 2.5邊緣終端保護結構 17 2.5.1 簡介與原理 17 2.5.2 邊緣終端保護結構種類 19 2.6垂直式雙擴散金氧半場效電晶體 22 2.6.1垂直式雙擴散金氧半場效電晶體的順向導通機制 22 2.6.2垂直式雙擴散金氧半場效電晶體的逆向崩潰機制 26 2.7超級接面 28 2.7.1超級接面的原理與結構 29 2.7.2 超級接面的製程方法 31 2.7.3超級接面在碳化矽金氧半場效電晶體的應用 33 第三章 模擬環境 34 3.1 模擬環境 34 3.2 模擬方法 35 第四章 金氧半場效電晶體模擬結果分析與討論 38 4.1元件初始設計 38 4.2 JFET寬度對元件電性之影響 45 4.3漂移區濃度對元件電性之影響 48 4.4閘極氧化層厚度對元件電性之影響 52 4.5超級接面結構對元件電性之影響 55 4.5.1改變漂移區濃度 61 4.5.2改變P pillar濃度(版本一) 63 4.5.3縮減P pillar寬度，改變P pillar濃度(版本二) 65 4.5.4縮減下層漂移區厚度，改變P pillar濃度(版本三) 67 4.5.5增加P pillar寬度，改變P pillar濃度(版本四) 69 4.6綜合比較 71 第五章 接面位障蕭基二極體光罩設計與製程 73 5.1光罩設計 73 5.2元件製程 78 5.2.1 實驗光罩流程 78 5.2.2 碳化矽晶圓參數 79 5.2.3 實驗製程步驟 80 第六章 接面位障蕭基二極體模擬與實驗結果討論 94 6.1 JBS元件電性模擬 94 6.2元件順向偏壓量測分析 102 6.2.1 JBS編號1、編號2、編號3、編號4順向偏壓特性比較 103 6.2.2 JBS編號1、編號5、編號6、編號7順向偏壓特性比較 104 6.3元件逆向偏壓量測分析 105 6.3.1 JBS編號1、編號2、編號3、編號4逆向偏壓特性比較 106 6.3.2 JBS編號1、編號2、編號3、編號4逆向偏壓特性比較 107 6.4綜合比較 108 第七章 結論與未來展望 110 參考文獻 112 | - |
| dc.language.iso | zh_TW | - |
| dc.title | 4H-SiC金氧半場效電晶體及接面位障蕭基二極體設計與製作 | zh_TW |
| dc.title | The Design and Fabrication of 4H-SiC Metal Oxide Semiconductor Field Effect Transistor and Junction Barrier Schottky Diode | en |
| dc.type | Thesis | - |
| dc.date.schoolyear | 108-1 | - |
| dc.description.degree | 碩士 | - |
| dc.contributor.oralexamcommittee | 黃智方;李佳翰 | zh_TW |
| dc.contributor.oralexamcommittee | Chih-Fang Huang;Jia-Han Li | en |
| dc.subject.keyword | 碳化矽,金氧半場效電晶體,超級接面,特徵導通電阻,崩潰電壓,接面位障蕭基二極體, | zh_TW |
| dc.subject.keyword | 4H-SiC,MOSFET,Super Junction,specific on-resistance,Breakdown Voltage,Junction Barrier Schottky Diode (JBS), | en |
| dc.relation.page | 114 | - |
| dc.identifier.doi | 10.6342/NTU201904378 | - |
| dc.rights.note | 未授權 | - |
| dc.date.accepted | 2019-12-10 | - |
| dc.contributor.author-college | 工學院 | - |
| dc.contributor.author-dept | 工程科學及海洋工程學系 | - |
| 顯示於系所單位： | 工程科學及海洋工程學系 | |
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