4096-QAM調變與解調器之研製與Ka頻段衛星相位陣列收發機模組系統設計

Abstract

本論文將分成兩個部分，第一個部分為寬頻調變器與解調器，裡面包含了E頻段寬頻直接升頻發射機以及38 GHz之具有高鏡像抑制之解調器，皆使用65 奈米互補式金屬氧化物半導體設計，另一部分則為由晶片等級進一步整合至系統等級之Ka頻段具有相位陣列之衛星通訊收發機模組。 在第一個部分的設計，由於使用次諧波混頻器架構的緣故，電路上會需要一個精準的45度產生器。而且因為希望可以有高資料量的傳輸，因此會使用高階調變來增加資料傳輸量。而在高階調變中，如何改善IQ路徑上的振福與相位平衡相當關鍵。在第一個電路中，我們在LO端提出了一個的45度產生器(HQG)。但考慮 到此結構對製程變異較為敏感。因此，也導入了製程變異容忍度分析的設計方法。它可以讓我們在設計上預測是否達到我們的要求，也藉以減輕製程變異的影響。此E頻段的發射機使用了5 dBm 的LO功率達成在56 至86 GHz之間有23±2 dB的增益。在1.2V的供應電壓下，直流功耗為164 mW且可具有6.5 dBm的輸出功率。此E頻段的高頻譜效率發射機並達到了在OFDM的訊號中，分別在1024-QAM與4096-QAM調變下分別具有1.6 %和1.58 %的誤差向量幅度。 另外，在第二個電路設計中，則是為了減少製程變異的問題，我們在LO端採用了一個基於傳輸線架構的分波器。跟傳統設計相比，這個設計對於製程變異較為不敏感。但相較於其他架構，所佔晶片面積會比較大，損耗也稍高。但是由於其對製程變異的影響較小，仍然是一個很好的選擇。此解調器在37.5 至41.5 GHz之間具有高達40 dBc的鏡像抑制能力。且在使用了6 dBm的LO功率達成在22 至41 GHz之間有2±2 dB的增益，在1.2V 的供應電壓下，直流功耗為75 mW。此38 GHz解調器也展示了在OFDM的訊號中，使用低中頻下分別在1024-QAM與4096-QAM調變下分別具有3.2 %和1.9 %的誤差向量幅度。 第二部分則是一個Ka 頻段中的衛星通訊收發模組的設計。此模組也同時結合了相位陣列的功能來達成天線波束的切換。對於系統應用的部分，除了各單一晶片的設計或是多功能晶片整合外，要如何將其使用到系統中是相當重要的一環。在這個設計中，我們由晶片等級提升至模組等級，最後再將其成功整合成完整系統。這對通訊系統原型的評估相當重要。在發射端使用29GHz，接收端使用19GHz的頻段來設計這個系統。升頻和降頻混頻器架構上使用於寬頻的鏡像抑制混波器，同時還能有合理的轉換增益以及直流功率消耗。前端電路部分還分別結合功率放大器與低雜訊放大器與相移器。全部皆以CMOS與砷化鎵製程來製作。最後，進一步並整合了電源供應系統、相位陣列的控制板與天線系統，使其具有可調訊號發射與接收方向的系統。同時，我們也做了類比與數位訊號測試來做系統的驗證。該系統在Ka頻段中提供了一種低成本，單極化相控陣列衛星通訊收發機，其具有34 dBm EIRP。在未來進一步小型化和整合之後，在可攜式衛星通訊模組應用中將具有很大的潛力。

This thesis will be divided into two parts. The first part is the wideband modulator and demodulator, which contains the E-band broadband direct up-conversion transmitter and the 38 GHz demodulator with high image rejection, respectively. These chips are all implemented in 65-nm CMOS process. The second part is a satellite communication transceiver module with a phased array that is integrated from the chip level to the system level at Ka-band. In the first part of the design, due to the application of the sub-harmonic architecture, a precise 45-degree generator will be needed in the circuit. Additionally, because the mixer is expected to have a higher throughput, a high-order modulation will be used to increase the data rate. In high-order modulation, it is quite critical lower the amplitude and phase imbalance on the IQ paths. In the first circuit, a 45-degree generator (half-quadrature generator, HQG) at the LO port is proposed. However, this structure is more sensitive to process variation. Therefore, the design methodology of process-variation tolerance analysis is also introduced. This allows us to predict whether we can meet our design requirements in design, so as to mitigate the impact of process variation.The E-band direct-conversion transmitter with a 5 dBm LO drive power provides a conversion gain of 23±2 dB from 56 to 86 GHz. The saturated power is 6.5 dBm with a total dc power consumption of 164 mW from a 1.2 V supply voltage. This spectrum-efficient transmitter achieves a 1024-QAM and 4096-QAM modulated signal with 1.6% and 1.58% EVM, respectively. In the second circuit design, in order to reduce the problem of process variation, we used a transmission-line based divider at the LO port. Compared with conventional techniques and architectures, this transmission-line based power splitter will have a larger chip area and slightly higher loss, but because this power splitter is less sensitive to process variation, it is still a good choice for this design. The demodulator achieves a high image rejection ratio of above 40 dBc from 37.5 to 41.5 GHz. It can also achieve 2±2 dB conversion gain from 22 to 41 GHz with 6 dBm LO power while consuming a total dc power consumption of 78 mW from the 1.0 V supply voltage. This demodulator also demonstrates a 1024-QAM and 4096-QAM modulated signal under the low IF operation with 3.2 % and 1.9 % EVM, respectively. The second part is the design of a Ka-band transceiver module with phased-array for satellite communication (SATCOM). This module combines the function of the phased-array to achieve beam switching of the antenna. For the system application, in addition to the design of each single chip and the integration of multi-chips (system on chip, SOC), it is also very important to know how to apply it in the system. In this design, we upgraded from the chip level to the module level, and finally successfully integrated it into a complete system. This is very important for the evaluation of the communication system prototype. The uplink and downlink frequency of this transceiver is 29GHz and 19GHz, respectively. Wideband image rejection mixers is adopted in the design of the up converter and down converter with low IF architectures, while also having reasonable conversion gain and dc power consumption. This system also includes the power amplifiers, low noise amplifiers and phase shifters in the front-end. This design uses the standard CMOS and GaAs phemt process with a compact chip size to realize the proposed transceiver system. Finally, this design also integrates the bias board, the controller of the phased array and the antenna system, so that it has adjustable signal transmission and reception directions. Analog and digital signal tests are simultaneously performed to verify the system. This system presents a low cost, single-polarized phased-array SATCOM transceiver in the Ka-band with a 34 dBm EIRP. After further miniaturization and integration in the future, it will have great potential in portable SATCOM applications.