V頻段功率放大器設計及Ka頻段衛星接收機之整合與測試

Abstract

資訊爆炸的現代，每個人都可以通過無線通信輕鬆訪問各種資訊。而隨著資訊量不斷地提升以及用戶不斷地增加，頻寬與傳輸速率的要求與日俱增。與第四代移動通信相比，第五代移動通信可以獲得更寬的帶寬和更高的數據速率，不僅適用於大資料量傳輸，還支持更高的用戶密度。除了sub-6GHz的使用外，在更高頻率中，將60 GHz設定為未來實際應用的頻段。而19 GHz及29 GHz則為衛星通訊的主要使用頻段。在無線通訊系統中，功率放大器與接收機的設計扮演著相當重要的部分，在本篇論文中，將著重於功率及衛星系統元件的設計，與衛星系統的整合。 本篇論文主要分為三個部分：第一部分(第二章)為一個應用於V頻段的功率毫米波放大器。該功率放大器以28 nm HPC+ CMOS製程實現，架構上用兩級與兩路結合的設計，以讓該電路能達到較高的輸出功率及輸出增益。其中，匹配網路皆以利用變壓器來完成，藉以有效縮小晶片面積。 第二部分(第三章)，為一個衛星通訊元件之設計。此章將介紹應用於K頻段的四倍器，該電路以180 nm CMOS製程實現，架構上採用兩個二倍頻器做串接，在第一個二倍頻器中採用電流再利用技術將二倍頻的訊號做放大，而在最後一級再串接一顆功率放大器將四倍頻放大，以達到設計目標。 第三部分(第四章)，為衛星通訊元件之整合，此章將會介紹如何將低雜訊放大器、移位器、混波器模組化，並自製電源整合模組將電壓源整合，並且利用數位控制電路來控制波束之方位。最後將介紹如何將這些模組整合並量測。

In the modern era of information explosion, everyone can easily access all kinds of information through wireless communication. As the amount of information continues to increase and users continue to increase, the requirements for bandwidth and transmission rate are increasing. Compared with the fourth-generation mobile communication, the fifth-generation mobile communication can obtain wider bandwidth and higher data rate, which is not only suitable for large data volume transmission, but also supports higher us-er density. In addition to the use of sub-6GHz, in the higher frequency, 60 GHz is set as the frequency band for practical application in the future. 19 GHz and 29 GHz are the main frequency bands used for satellite communications. In wireless communication sys-tems, the design of power amplifiers and receivers plays a very important part. In this pa-per, we will focus on the design of power and satellite system components and integration with satellite systems. This paper is mainly divided into three parts: The first part (Chapter 2) is a power millimeter wave amplifier applied in the V-band. The power amplifier is implemented in a 28 nm HPC+ CMOS process. The architecture uses a two-stage and two-way design to allow the circuit to achieve higher output power and output gain. Among them, the matching network is completed by using a converter to effectively reduce the chip area. The second part (Chapter 3) is the design of a satellite communication component. This chapter will introduce a quadruple applied to the K-band. The circuit is implemented in a 180 nm CMOS process. The architecture uses two doublers for series connection. In the first doubler, current reuse technology will be used. The double frequency signal is amplified, and a power amplifier is connected in series at the last stage to amplify the fourth frequency to achieve the design goal. The third part (Chapter 4) is the integration of satellite communication components. This chapter will introduce how to modularize low noise amplifiers, shifters, mixers, and self-made dc integration modules to convert the voltage Source integration, and the use of digital control circuit to control the beam orientation. Finally, we will introduce how to integrate and measure these modules.