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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 黃天偉(Tian-Wei Huang) | |
| dc.contributor.author | Yan-Ting Lu | en |
| dc.contributor.author | 盧彥廷 | zh_TW |
| dc.date.accessioned | 2021-07-10T21:37:23Z | - |
| dc.date.available | 2021-07-10T21:37:23Z | - |
| dc.date.copyright | 2020-08-28 | |
| dc.date.issued | 2020 | |
| dc.date.submitted | 2020-08-18 | |
| dc.identifier.citation | [1]K. Guo, P. Huang, K. Kang “A 60-GHz 1.2 V 21 dBm power amplifier with a fully symmetric 8-way transformer power combiner in 90 nm CMOS,” in IEEE MTT-S Int. Microw. Symp. Dig., June 2014. [2]R. Ciocoveanu, R. Weigel, A. Hagelauer and V. Issakov, 'Design of a 60 GHz 32% PAE Class-AB PA with 2nd Harmonic Control in 45-nm PD-SOI CMOS,' in IEEE Transactions on Circuits and Systems I: Regular Papers. [3]J. Xia, X.-H. Fang, and S. Boumaiza, “60-GHz power amplifier in 45-nm SOI-CMOS using stacked transformer-based parallel power combiner,”IEEE Mi-crow. Wireless Compon. Lett., vol. 28, no. 8, pp. 711–713, Aug. 2018. [4]P. Masoumi Farahabadi and K. Moez, “A dual-mode wideband +17.7-dBm 60-GHz power amplifier in 65-nm CMOS,” IEEE Trans. Compon.,Packag., Manuf. Tech-nol., vol. 7, no. 12, pp. 1998–2007, Dec. 2017 [5]K. Ning and J. F. Buckwalter, “An 18-dBm, 57 to 85-GHz, 4-stack FET power am-plifier in 45-nm SOI CMOS,” in IEEE MTT-S Int. Microw.Symp. Dig., Jun. 2018, pp. 1453–1456. [6]M. Bassi, et al., “A 40–67 GHz power amplifier with 13 dBm Psat and 16% PAE in 28 nm CMOS LP,” IEEE J. Solid-State Circuits, vol. 50, no. 7, pp. 1618-1628, Jul. 2015. [7]B. Park, Daechul Jeong, J. Kim, Y. Cho, Kyunghoon Moon and B. Kim, “Highly linear CMOS power amplifier for mm-wave applications,” in IEEE MTT-S Int. Mi-crow. Symp. Dig., May 2016, pp. 1-3. [8]E. Monaco, M. Pozzoni, F. Svelto and A. Mazzanti, 'Injection-Locked CMOS Fre-quency Doublers for u-Wave and mm-Wave Applications,' in IEEE Journal of Sol-id-State Circuits, vol. 45, no. 8, pp. 1565-1574, Aug. [9]F. Gruson, G. Bergmann, and H. Schumacher, “A frequency doubler with high conversion gain and good fundamental suppression,” in IEEE MTT-S Int. Dig., Jun. 2004, vol. 1, pp. 175–178. [10]S. A. Maas, Nonlinear Microwave and RF Circuits, 2nd ed. Norwell, MA: Artech House, 1997, pp. 475–495. [11]K. Y. Lin, J. Y. Huang, and S. C. Shin, “A K-band CMOS distributed doubler with current-reuse technique,” IEEE Mircow. Wireless Compon. Lett., vol. 19, no. 5, pp. 308–310, May 2009 [12]K. Y. Lin, J. Y. Huang, J. L. Kuo, C. S. Lin, and H. Wang, “A 14 ~ 23 GHz CMOS MMIC distributed doubler with a 22-dB fundamental rejection,” in IEEE MTT-S Int. Dig., Jun. 2008, vol. 15–20, pp.1477–1480. [13]K. Yamamoto, “A 1.8-V operation 5-GHz-band CMOS frequency doubler using current-reuse circuit design technique,” IEEE J. Solid State Circuits, vol. 40, no. 6, pp. 1288–1295, Jun. 2005 [14]Yu-Ci Li, ' Design and Integration of Mixer for 5G Mobile System and Satellite Communication Applications,' M.S. thesis, National Taiwan University, Taipei, Taiwan, 2018 [15]Wu-Chen Lin, ' Design and Research of Key Components of Transmitter for 5G and Satellite Communication System,' M.S. thesis, National Taiwan University, Taipei, Taiwan, 2018. [16]Wei-Pang Chao, ' Design and Analysis of Millimeter-Wave Power Amplifier,' M.S. thesis, National Taiwan University, Taipei, Taiwan, 2018. [17]蕭劭丞撰，應用於物聯網和第五代行動通訊之低功耗低雜訊放大器和接收器與發射器之設計與研究，國立台灣大學電信工程研究所碩士論文，2017 年 7 月。 | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/76805 | - |
| dc.description.abstract | 資訊爆炸的現代，每個人都可以通過無線通信輕鬆訪問各種資訊。而隨著資訊量不斷地提升以及用戶不斷地增加，頻寬與傳輸速率的要求與日俱增。與第四代移動通信相比，第五代移動通信可以獲得更寬的帶寬和更高的數據速率，不僅適用於大資料量傳輸，還支持更高的用戶密度。除了sub-6GHz的使用外，在更高頻率中，將60 GHz設定為未來實際應用的頻段。而19 GHz及29 GHz則為衛星通訊的主要使用頻段。在無線通訊系統中，功率放大器與接收機的設計扮演著相當重要的部分，在本篇論文中，將著重於功率及衛星系統元件的設計，與衛星系統的整合。 本篇論文主要分為三個部分：第一部分(第二章)為一個應用於V頻段的功率毫米波放大器。該功率放大器以28 nm HPC+ CMOS製程實現，架構上用兩級與兩路結合的設計，以讓該電路能達到較高的輸出功率及輸出增益。其中，匹配網路皆以利用變壓器來完成，藉以有效縮小晶片面積。 第二部分(第三章)，為一個衛星通訊元件之設計。此章將介紹應用於K頻段的四倍器，該電路以180 nm CMOS製程實現，架構上採用兩個二倍頻器做串接，在第一個二倍頻器中採用電流再利用技術將二倍頻的訊號做放大，而在最後一級再串接一顆功率放大器將四倍頻放大，以達到設計目標。 第三部分(第四章)，為衛星通訊元件之整合，此章將會介紹如何將低雜訊放大器、移位器、混波器模組化，並自製電源整合模組將電壓源整合，並且利用數位控制電路來控制波束之方位。最後將介紹如何將這些模組整合並量測。 | zh_TW |
| dc.description.abstract | In the modern era of information explosion, everyone can easily access all kinds of information through wireless communication. As the amount of information continues to increase and users continue to increase, the requirements for bandwidth and transmission rate are increasing. Compared with the fourth-generation mobile communication, the fifth-generation mobile communication can obtain wider bandwidth and higher data rate, which is not only suitable for large data volume transmission, but also supports higher us-er density. In addition to the use of sub-6GHz, in the higher frequency, 60 GHz is set as the frequency band for practical application in the future. 19 GHz and 29 GHz are the main frequency bands used for satellite communications. In wireless communication sys-tems, the design of power amplifiers and receivers plays a very important part. In this pa-per, we will focus on the design of power and satellite system components and integration with satellite systems. This paper is mainly divided into three parts: The first part (Chapter 2) is a power millimeter wave amplifier applied in the V-band. The power amplifier is implemented in a 28 nm HPC+ CMOS process. The architecture uses a two-stage and two-way design to allow the circuit to achieve higher output power and output gain. Among them, the matching network is completed by using a converter to effectively reduce the chip area. The second part (Chapter 3) is the design of a satellite communication component. This chapter will introduce a quadruple applied to the K-band. The circuit is implemented in a 180 nm CMOS process. The architecture uses two doublers for series connection. In the first doubler, current reuse technology will be used. The double frequency signal is amplified, and a power amplifier is connected in series at the last stage to amplify the fourth frequency to achieve the design goal. The third part (Chapter 4) is the integration of satellite communication components. This chapter will introduce how to modularize low noise amplifiers, shifters, mixers, and self-made dc integration modules to convert the voltage Source integration, and the use of digital control circuit to control the beam orientation. Finally, we will introduce how to integrate and measure these modules. | en |
| dc.description.provenance | Made available in DSpace on 2021-07-10T21:37:23Z (GMT). No. of bitstreams: 1 U0001-1708202017133300.pdf: 18148884 bytes, checksum: 9815658b46f224e915cea6da5a961a51 (MD5) Previous issue date: 2020 | en |
| dc.description.tableofcontents | 致謝 i 中文摘要 iii ABSTRACT iv CONTENTS vi LIST OF FIGURES ix LIST OF TABLES xvi Chapter 1 Introduction 17 1.1 Background and Motivation 17 1.2 Thesis Organization 18 Chapter 2 Design of V-Band Power Amplifiers in 28-nm HPC Plus CMOS process 19 2.1 Introduction 19 2.2 Circuit Design 21 2.2.1 Proposed Power Amplifier Architecture 21 2.2.2 Power Stage Design 22 2.2.3 Output Stage Design 30 2.2.4 Driver Stage Design 32 2.2.5 Simulation Results 35 2.3 Experimental Results 39 2.3.1 Continuous-wave Measurement Results 39 2.3.2 Comparison Table 43 2.3.3 Discussion and Summary 43 Chapter 3 Design of K-Band Quadrupler in 180-nm CMOS process for Satellite Receiver 45 3.1 Introduction 45 3.2 Circuit Design 46 3.2.1 Proposed quadrupler architecture 46 3.2.2 First stage doubler 47 3.2.3 Second stage doubler 50 3.2.4 Simulation Results 53 3.3 Experimental Results 56 3.3.1 Continuous-wave Measurement Results 56 3.3.2 Discussion and Summary 60 Chapter 4 Ka-band satellite receiver integration and testing 61 4.1 Introduction 61 4.2 The second version of satellite receiver introduction 62 4.3 Chip introduction and implementation of modules 66 4.3.1 Voltage Board with STM32 66 4.3.2 GaAs Low Noise Amplifier 75 4.3.3 CMOS phase shifter 82 4.3.4 CMOS Power Combiner 88 4.3.5 CMOS Low Noise Amplifier 93 4.3.6 Down-mixer 97 4.4 The third version of satellite receiver introduction 103 4.5 Experimental results of the second version of satellite receiver 113 4.6 Experimental results of the third version of satellite receiver 120 4.7 Future Work. 126 Chapter 5 Summary 128 References 130 | |
| dc.language.iso | en | |
| dc.subject | 倍頻器 | zh_TW |
| dc.subject | 互補式金氧半導體 | zh_TW |
| dc.subject | 毫米波 | zh_TW |
| dc.subject | 功率放大器 | zh_TW |
| dc.subject | 衛星通訊系統 | zh_TW |
| dc.subject | satellite communication system | en |
| dc.subject | CMOS | en |
| dc.subject | millimeter-wave | en |
| dc.subject | multiplier | en |
| dc.subject | power amplifier | en |
| dc.title | V頻段功率放大器設計及Ka頻段衛星接收機之整合與測試 | zh_TW |
| dc.title | V-band power amplifier design and integration and testing of Ka-band satellite receiver | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 108-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 蔡政翰(Jeng-Han Tsai),鍾杰穎(Jie-Ying Zhong) | |
| dc.subject.keyword | 互補式金氧半導體,毫米波,功率放大器,衛星通訊系統,倍頻器, | zh_TW |
| dc.subject.keyword | CMOS,millimeter-wave,power amplifier,satellite communication system,multiplier, | en |
| dc.relation.page | 132 | |
| dc.identifier.doi | 10.6342/NTU202003814 | |
| dc.rights.note | 未授權 | |
| dc.date.accepted | 2020-08-19 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電信工程學研究所 | zh_TW |
| 顯示於系所單位： | 電信工程學研究所 | |
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|---|---|---|---|
| U0001-1708202017133300.pdf 未授權公開取用 | 17.72 MB | Adobe PDF |
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