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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/7635完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 呂良鴻(Liang-Hung Lu) | |
| dc.contributor.author | Yu-Kai Tsai | en |
| dc.contributor.author | 蔡渝楷 | zh_TW |
| dc.date.accessioned | 2021-05-19T17:48:36Z | - |
| dc.date.available | 2023-02-23 | |
| dc.date.available | 2021-05-19T17:48:36Z | - |
| dc.date.copyright | 2018-02-23 | |
| dc.date.issued | 2018 | |
| dc.date.submitted | 2018-01-29 | |
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/7635 | - |
| dc.description.abstract | 近年來自動化生產以及物聯網相關的應用在業界與學界掀起了一陣旋風，為了實現這些功能，大量的感測器端點扮演了不可或缺的角色。為了減少端點之間的連結的困難，勢必得利用無線傳輸進行端點間的溝通或資料的傳輸。這些端點通常會使用電池或是從外界環境進行能量擷取，而如何降低端點功耗來延長電池壽命或增加能量擷取的效率便成了一個重要的課題。一般來說，無線收發端需要消耗較多的能量，然而可以靠縮短其工作周期減低其平均消耗功率。此時，在感測器端點內持續操作不間斷的電路消耗了大部分的能量，在本論文中，挑選了其中兩種電路：時脈產生器與感測器介面電路在90奈米互補式金氧半製程使用具備效率優勢的弛張振盪器進行實做。
首先，對於一個做為時脈產生器的弛張振盪器，其比較器隨著溫度變化的延遲時間是實現一個高頻率對溫度穩定度的最大難題。本論文提出了一個累積誤差迴授技巧搭配上組合溫度係數相反的電阻，成功實現出一振盪頻率為51.3 MHz，等效溫度係數為21.8 ppm/°C且溫度操作範圍為-20°C至100°C的弛張振盪器。此振盪器當供應電壓由0.8 V變化至1.2 V時相對應的頻率變化為±0.53 %。 本論文接下來將基於振盪器架構實現的時間模式積分微分調變電容數位轉換器依據其數位輸出與振盪器的周期或是頻率成正比來簡單區分為周期型與頻率型。首先闡述了周期型架構的操作原理與雜訊來源的數學分析，並藉由一個循序搜尋頻率校準電路來解決振盪器頻率隨製程變異飄移的問題，成功實現一個等效解析度為8.8位元，品質因數為1.16 pJ/c.-s.的電容數位轉換器。同時也實做了頻率型電容數位轉換器用以比較，藉由分析非線性誤差產生的來源，本論文提出了一個非線性誤差補償技巧。此頻率型電容數位轉換器等效解析度為7.9位元，品質因數為10.6 pJ/c.-s.。最後則提出了對於上述電路實做之心得以及比較作為結論。 | zh_TW |
| dc.description.abstract | As the dramatically increase of the number of sensor nodes in the future wireless sensor network for Internet of things or factory automation, lowering the power consumption of each sensor node becomes an important issue. In this thesis, two essential blocks of a typical wireless sensor node are chosen and realized with energy-efficient relaxation oscillators in a 90-nm general-purpose CMOS process. To begin with, a 51.3-MHz CMOS relaxation oscillator is implemented. By pointing out the main challenge of achieving high frequency stability versus temperature is the delay time variation of the comparator, an integrated error feedback (IEF) is proposed to conquer the challenge. Due to the use of the proposed IEF technique and composite resistors, the fabricated circuit demonstrates an average frequency drift of 21.8 ppm/°C for a temperature range from -20 to 100°C. As the supply voltage changes from 0.8 to 1.2 V, the frequency variation is ±0.53%. It is well suited for emerging applications where low-power operations are required. Then, a period-mode oscillator-based capaci-tance-to-digital converter (CDCs) is implemented. With the help of the comprehensive analysis of the noise contribution and the sequential search frequency calibration (SSFC), the CDC achieves an equivalent bits of resolution of 8.8 bit with an FoM of 1.16 pJ/c.-s. for off-chip capacitance ranging from 0 to 15 pF. Furthermore, a frequency-mode oscillator-based capacitance-to-digital converter (CDCs) is implemented for comparison. A linearity compensation method is adopted by considering all causes of nonlinearity in detail. As the result, a highly linear performance can be expected when facing on-chip capacitive sensors or connecting the sensor and the CDC directly by bond wires. The frequency-mode CDC demonstrates an equivalent bits of resolution of 7.9 bit with an FoM of 10.6 pJ/c.-s. for an off-chip capacitance ranging from 0 to 12 pF. Finally, a conclusion of oscillator-based circuits is given. | en |
| dc.description.provenance | Made available in DSpace on 2021-05-19T17:48:36Z (GMT). No. of bitstreams: 1 ntu-107-F98943004-1.pdf: 8227612 bytes, checksum: dff860e95750559420fd3eaa9eb425ea (MD5) Previous issue date: 2018 | en |
| dc.description.tableofcontents | 致謝 i
摘要 iii ABSTRACT iv LIST OF FIGURES ix LIST OF TABLES xii CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 2 CHAPTER 2 A TEMPERATURE COMPENSATED CMOS RELAXATION OSCILLATOR 3 2.1 MOTIVATION AND SPECIFICATION OF CLOCK SIGNALS 3 2.1.1 Frequency stability of Sleep-Time Clocks 4 2.1.2 Sampling clock jitter of data converter 5 2.1.3 Frequency tolerance in wireless transceivers 6 2.2 TECHNIQUES FOR GENERATING A STABLE CLOCK SIGNAL 7 2.3 THE PROPOSED 51.3-MHZ 21.8-PPM/°C CMOS RELAXATION OSCILLATOR 9 2.3.1 Overview of Operation 9 2.3.2 Integrated Error Feedback (IEF) 10 2.3.3 Sampling Capacitor CS 14 2.3.4 Generation of the Reference 14 2.4 EXPERIMENTAL RESULTS 18 2.5 SUMMARY 21 CHAPTER 3 BACKGROUND OF CAPACITIVE SENSOR INTERFACE CIRCUITS 23 3.1 CAPACITIVE SENSORS 23 3.2 STATE-OF-THE-ART TECHNIQUES FOR INTERFACE CIRCUITS 24 3.3 IMPORTANT PARAMETERS OF INTERFACE CIRCUITS 25 3.3.1 Input Capacitance Range 25 3.3.2 Sampling frequency / Conversion Time 25 3.3.3 Capacitance Resolution 26 3.3.4 Linearity 26 3.3.5 Power Consumption 26 3.4 PRINCIPLES OF OSCILLATOR-BASED CDC: PERIOD MODE & FREQUENCY MODE 26 CHAPTER 4 A PERIOD-MODE OSCILLATOR-BASED CAPACITOR-TO-DIGITAL CONVERTER 29 4.1 OVERVIEW OF OPERATION 29 4.2 NON-IDEAL EFFECTS 33 4.2.1 Jitter of CCO 33 4.2.2 Jitter of CLK 33 4.2.3 Jitter of RCO 33 4.2.4 Period Deviation between k∙TCLK and TRCO 34 4.2.5 Leakage and Dead-Zone of the Gated RCO 35 4.2.6 Estimated SNR with Non-Ideal Effects 36 4.3 CIRCUIT IMPLEMENTATION OF THE PROPOSED CDC 37 4.3.1 Capacitor-Controlled Oscillator 37 4.3.2 Gated RCO 40 4.3.3 Sequential Search Frequency Calibration 42 4.3.4 Residue Generator and Counters 46 4.4 MEASUREMENT RESULTS 47 4.5 SUMMARY 53 CHAPTER 5 A FREQUENCY-MODE OSCILLATOR-BASED CAPACITOR-TO-DIGITAL CONVERTER 55 5.1 OVERVIEW OF OPERATION 55 5.2 CIRCUIT IMPLEMENTATION OF THE PROPOSED CDC 59 5.2.1 C-to-V Converter and VCO1 59 5.2.2 Gated VCO2 61 5.2.3 Implementation of Iint and opamps 62 5.2.4 Residue Generator and Counters 63 5.3 NON-IDEAL EFFECTS FOR NOISE CONSIDERATION 63 5.3.1 Jitter of CLK 64 5.3.2 Jitter of VCO1 64 5.3.3 Jitter of VCO2 64 5.3.4 Frequency mismatch between VCO1 and VCO2 65 5.3.5 Estimated SNR with Jitter and Frequency Deviation 66 5.4 NON-IDEAL EFFECTS FOR LINEARITY CONSIDERATION 67 5.4.1 Delay Time of the Comparator and Digital Blocks 67 5.4.2 Leakage Current of the Reset Switch in VCO1 69 5.4.3 Finite Output Impedance of Iint 71 5.4.4 Leakage Current of the Switches in C2V 72 5.5 MEASUREMENT RESULTS 74 5.6 SUMMARY 83 CONCLUSION 85 REFERENCE 87 PUBLICATION LIST 95 | |
| dc.language.iso | en | |
| dc.title | 在低功耗無線感測應用中弛張振盪器的運用法 | zh_TW |
| dc.title | Utilization of Relaxation Oscillators in Low-Power Wireless Sensing Applications | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 106-1 | |
| dc.description.degree | 博士 | |
| dc.contributor.oralexamcommittee | 鄭國興(Kuo-Hsing Cheng),陳巍仁(Wei-Zen Chen),林宗賢(Tsung-Hsien Lin),黃俊郎(Jiun-Lang Huang) | |
| dc.subject.keyword | 弛張震盪器,低功耗,感測器介面, | zh_TW |
| dc.subject.keyword | relaxation oscillator,low power,sensor interface,time-mode noise-shaping, | en |
| dc.relation.page | 95 | |
| dc.identifier.doi | 10.6342/NTU201800190 | |
| dc.rights.note | 同意授權(全球公開) | |
| dc.date.accepted | 2018-01-29 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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