適用於生醫應用之生物訊號擷取類比前端電路設計

Abstract

本論文實作並量測一個晶片，此晶片適用於腦波偵測的低雜訊與低功耗類比前端電路。此前端電路的架構使用電流回授儀表放大器，並利用動態偏移補償技術，以截波之方式達到去除閃爍雜訊的效果。此電路亦包含一個漣波抑制電路，能將截波技術產生的漣波消除。本電路使用了兩種不同的方式來抑制因電極不匹配而造成的偏移電壓。第一種方式是利用交換電容積分器，以負回授補償的方式來消除偏移電壓，量測結果顯示電路具有高通濾波的效果。然而因為交換電容電路的雜訊折疊效應，影響了低頻訊號的品質。第二種方式是使用極短的工作週期，將電阻的低阻值提升至高阻抗。藉由此一特性，實現高通濾波的效果，並在低頻率也有良好的表現。這顆晶片實作於台積電180奈米製程，晶片核心面積為0.56平方毫米。此電路在1.8伏特下消耗28.7微安培的電流，在局部場電位頻帶(1到200赫茲)中，積分雜訊為1.275微伏特，在動作電位(200到5千赫茲)頻帶中，積分雜訊則為3.675微伏特。雜訊效率比分別為18.65和10.95。

This thesis introduces the design of analog front-end circuits for biomedical application. The front-end is based on a chopper CFIA, with a ripple reduction loop and a DC servo loop. Chopping technique is employed to suppress the flicker noise and offset. The output ripple introduced by chopping is suppressed by ripple reduction loop. In bio-medical applications, the high-pass corner frequency should be set under 1 Hz, which requires a large time constant integrator. We implement two kinds of integrators, both structures are area-efficient, and avoid using pseudo-resistors and off-chip capacitors. The switched-capacitor integrator achieves a high-pass corner of 0.2 Hz. However, the aliasing issue in switched-capacitor can cause severely aliased noise in low frequency, which degrades the noise performance. On the other hand, integrator using duty-cycled resistor has the better noise performance in low frequency. The chip is implemented with TSMC 180-nm process and the core area is 0.56 mm2. With current consumption of 27.83 uA, the input-referred noise in the LFP signal band (1 Hz-200 Hz) and AP signal band (200 Hz-5 kHz) are 1.275 uVrms and 3.675 uVrms, respectively. The NEF can be calculated as 18.65 and 10.95, respectively.