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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/74188完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 林宗賢(Tsung-Hsien Lin) | |
| dc.contributor.author | Yang-Sheng Cheng | en |
| dc.contributor.author | 鄭揚聲 | zh_TW |
| dc.date.accessioned | 2021-06-17T08:23:33Z | - |
| dc.date.available | 2020-08-18 | |
| dc.date.copyright | 2019-08-18 | |
| dc.date.issued | 2019 | |
| dc.date.submitted | 2019-08-13 | |
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/74188 | - |
| dc.description.abstract | 本論文實作並量測一個晶片，此晶片適用於腦波偵測的低雜訊與低功耗類比前端電路。此前端電路的架構使用電流回授儀表放大器，並利用動態偏移補償技術，以截波之方式達到去除閃爍雜訊的效果。此電路亦包含一個漣波抑制電路，能將截波技術產生的漣波消除。本電路使用了兩種不同的方式來抑制因電極不匹配而造成的偏移電壓。第一種方式是利用交換電容積分器，以負回授補償的方式來消除偏移電壓，量測結果顯示電路具有高通濾波的效果。然而因為交換電容電路的雜訊折疊效應，影響了低頻訊號的品質。第二種方式是使用極短的工作週期，將電阻的低阻值提升至高阻抗。藉由此一特性，實現高通濾波的效果，並在低頻率也有良好的表現。這顆晶片實作於台積電180奈米製程，晶片核心面積為0.56平方毫米。此電路在1.8伏特下消耗28.7微安培的電流，在局部場電位頻帶(1到200赫茲)中，積分雜訊為1.275微伏特，在動作電位(200到5千赫茲)頻帶中，積分雜訊則為3.675微伏特。雜訊效率比分別為18.65和10.95。 | zh_TW |
| dc.description.abstract | This thesis introduces the design of analog front-end circuits for biomedical application. The front-end is based on a chopper CFIA, with a ripple reduction loop and a DC servo loop. Chopping technique is employed to suppress the flicker noise and offset. The output ripple introduced by chopping is suppressed by ripple reduction loop. In bio-medical applications, the high-pass corner frequency should be set under 1 Hz, which requires a large time constant integrator. We implement two kinds of integrators, both structures are area-efficient, and avoid using pseudo-resistors and off-chip capacitors. The switched-capacitor integrator achieves a high-pass corner of 0.2 Hz. However, the aliasing issue in switched-capacitor can cause severely aliased noise in low frequency, which degrades the noise performance. On the other hand, integrator using duty-cycled resistor has the better noise performance in low frequency. The chip is implemented with TSMC 180-nm process and the core area is 0.56 mm2. With current consumption of 27.83 uA, the input-referred noise in the LFP signal band (1 Hz-200 Hz) and AP signal band (200 Hz-5 kHz) are 1.275 uVrms and 3.675 uVrms, respectively. The NEF can be calculated as 18.65 and 10.95, respectively. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-17T08:23:33Z (GMT). No. of bitstreams: 1 ntu-108-R05943104-1.pdf: 8294535 bytes, checksum: bf9169bba8e0654c2722d63f41aae9e1 (MD5) Previous issue date: 2019 | en |
| dc.description.tableofcontents | 中文審定書 iii
英文審定書 v 摘要 ix Abstract xi List of Figures xvi List of Tables xxi Chapter 1 Introduction 1 1.1 Background 1 1.2 Dissertation Overview 2 Chapter 2 Fundamental of Sensor Interface Circuits 3 2.1 Basic Sensor Read-Out Systems 3 2.2 Non-Idealities in Sensor Read-Out Systems 7 2.2.1 Offset Voltage 7 2.2.2 Noise 9 2.2.3 Common-Mode Variation 11 2.3 Dynamic Offset Compensation Technique 12 2.3.1 Auto-zeroing 12 2.3.2 Chopping 14 Chapter 3 Design of a Chopper CFIA with a Ripple Reduction Loop for EEG Application 17 3.1 Introduction 17 3.2 System Architecture 19 3.2.1 Behavior Model of CFIA 20 3.2.2 Behavior Model of Chopper CFIA 22 3.2.3 Behavior Model of Ripple Reduction Loop (RRL) 26 3.3 Transistor Level Design and Simulation Result 33 3.3.1 Input Stage of CFIA 34 3.3.2 Output Stage of CFIA 38 3.3.3 Cascode Buffers 41 3.4 System Level Simulation Results 44 3.5 Measurement Results 51 3.5.1 Chip Configuration and Die Photo 51 3.5.2 Measurement Environment Setup 52 3.5.3 Offset of CFIA 54 3.5.4 Frequency Response of CFIA 55 3.5.5 Noise Response 56 3.5.6 CMRR 57 3.5.7 RRL Measured Results 58 3.5.8 Total Harmonic Distortion 59 3.5.9 Input Impedance 61 3.6 Discussion and Summary 62 Chapter 4 Design of a Chopper CFIA with a DC Servo Loop for EEG Application Using Switched-Capacitor Integrator 65 4.1 Introduction 65 4.2 System Architecture 67 4.2.1 Behavior Model of DC Servo Loop (DSL) 67 4.2.2 Noise and Offset Analysis in DSL 70 4.2.3 Behavior Model of Switched-Capacitor Integrator 71 4.3 Transistor Level Design and Simulation Result 75 4.3.1 Feedback Resistor and Input Stage of CFIA 75 4.3.2 Switched-Capacitor Integrator 76 4.4 System Simulation Results 80 4.5 Measurement Results 82 4.5.1 Frequency Response 82 4.5.2 Noise Response 83 4.5.3 Total Harmonic Distortion 86 4.6 Discussion and Summary 87 Chapter 5 Design of a Chopper CFIA with a DC Servo Loop for EEG Application Using Duty-Cycled Resistor 89 5.1 Introduction 89 5.2 System Architecture 90 5.2.1 Behavior Model of Duty-Cycled Resistor 90 5.2.2 Noise Analysis of Duty-Cycled Resistor Integrator 92 5.3 Transistor Level Design and Simulation Result 94 5.3.1 Duty-cycled Resistor Integrator 95 5.3.1 System Simulation Results 102 5.4 Measurement Result 104 5.4.1 Frequency Response 104 5.4.2 Noise Response 106 5.4.3 Total Harmonic Distortion 108 5.5 Discussion and Summary 110 5.6 Comparison with State-Of-The-Art 112 Chapter 6 Conclusions and Future Works 114 6.1 Conclusions 114 6.2 Future Works 115 References 117 | |
| dc.language.iso | en | |
| dc.title | 適用於生醫應用之生物訊號擷取類比前端電路設計 | zh_TW |
| dc.title | Design of Bio-signal Acquisition Front-End Circuits for Biomedical Application | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 107-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.coadvisor | 呂學士(Shey-Shi Lu) | |
| dc.contributor.oralexamcommittee | 黃柏鈞,彭盛裕,李泰成 | |
| dc.subject.keyword | 低功率,低雜訊,感測器,類比前端電路,儀表放大器,生醫應用, | zh_TW |
| dc.subject.keyword | Low Power,Low Noise,Sensor,Analog Front-End Circuits,Instrumentation Amplifier,Biomedical Applications, | en |
| dc.relation.page | 121 | |
| dc.identifier.doi | 10.6342/NTU201903112 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2019-08-13 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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