二值化神經網路之邏輯合成

Abstract

類神經網路是深度學習技術中的核心。因此，如何有效率地在硬體上佈署神經網路對深度學習的實際應用影響深遠。在類神經網路中，二值化神經網路是最近被提出的一種特殊的神經網路，其中每個神經權重的輸出都被二值化成{-1,+1}(也可在硬體中編碼成{0,1})。不同於一般浮點數的模型需要乘法器，二值化神經網路可以改使用互斥或電路來實現，因而特別適合硬體實現。在此神經網路的研究上，前人主要將資料與權重都讀入神經網路處理單位，這樣的方法雖然使用的硬體資源量較少，卻需要更多量的記憶體讀取，也可能導致能量與效能上的劣勢。在這份研究中，我們將二值化神經網路視為邏輯電路，探討其在硬體資源上的邏輯合成優化，並將此優化問題定義為神經網路剪枝與矩陣覆蓋問題。在神經網路剪枝方面，根據前人的成果我們提出了三種策略與其評量方式；在矩陣覆蓋上面，我們提出了一有效率的演算法以減少繞線成本。藉由融合這兩種方法，實驗結果證實我們可以有效地減少使用的硬體資源。在二值化神經網路的硬體實現方面，相對於原先的神經網路處理單位方法，我們提供了一種可以並行的替代方案，以達成在面積、效能、功率上的取捨。

Neural networks (NNs) are key to deep learning systems. Their efficient hardware implementation is crucial to applications at the edge. Binarized NNs (BNNs), where the weights and output of a neuron are of binary values {-1, +1} (or encoded in {0, 1}), have been proposed recently. As no multiplier required, binarized neural networks are particularly attractive and suitable for hardware realization. Most prior NN synthesis methods target on hardware architectures with neural processing elements (NPEs), where the weights of a neuron are loaded and the output of the neuron is computed. The load-and-compute method, though area efficient, requires expensive memory access, which deteriorates energy and performance efficiency. In this work we aim at synthesizing BNN layers into dedicated logic circuits. We formulate the corresponding model pruning problem and matrix covering problem to reduce the area and routing cost of BNNs. For model pruning, we propose three strategies according to previous works and an evaluation topology to prune model at training stage. For matrix covering, we propose a scalable algorithm to reduce the area and routing cost of BNNs. By combining these two methods, experimental results justify the effectiveness of the method in terms of area and net savings on FPGA implementation. Our method provides an alternative implementation of BNNs, and can be applied in combination with NPE-based implementation for area, speed, and power tradeoffs.