0.18 um CMOS中心式數位脈波寬度調變器設計

Abstract

隨著手機不斷進步、科技不斷發展，現今對於通話品質的要求越來越高，此時手機中的極發射器就需要更好的效能。因此極發射器中的E類功率放大器的控制電路「中心式數位脈波寬度調變器」漸漸需要提供高頻率、高解析度的脈波輸出。為了實現中心式數位脈波寬度調變器，本論文使用延遲鎖相迴路產生128組相位，再使用查找表搭配多工器、邏輯閘產生出脈波寬度調變訊號。透過使用延遲鎖相迴路，可以精準的產生脈波相位，並且受到製程、電壓、溫度變異的影響也較小。 本論文使用TSMC 0.18 um CMOS製程實作七位元中心式數位脈波寬度調變器，操作頻率為100 MHz，最小脈波寬度為78 ps。整體晶片面積為0.979×0.6 〖mm〗^2，總功耗約為20 mW，扣除輸出級電路的功耗約為2 mW。最後的可量測PWM 工作範圍為3 % ~ 96 %，INL則落在-1.08 ~ 1.28 LSB之間，DNL落在-0.48 ~ 0.73 LSB之間。本論文使用自行設計之前緣組合電路來將降低責任週期對整體電路的輸出影響，透過量測結果證明此項設計是可行的。在PMPT應用方面，對64-QAM的20M LTE訊號進行處理，將振幅訊號轉為PWM訊號，輸出至晶片進行量測，ACLR的量測結果為15 dBc。

With the advancement of the mobile phone applications and the development of the technology, the quality of the phone call gets higher than before. It requires the polar transmitter in the mobile system better performance. As a result, digital pulse width modulator applied to class E PA in polar transmitter of cellular phone needs to provide output pulse of high frequency as well as high resolution. This thesis presents a CMOS digital pulse width modulator (DPWM) architecture. This DPWM uses a delay-locked loop (DLL) to generated 128 phases. Look-up table, multiplexers and logic gates are used to combine these phases into PWM signals. With the help of the delay-locked loop, the pulse phase can be generated accurately and less affected by the variations of process, voltage, and temperature. This thesis presents a 7-bit centered DPWM fabricated in a TSMC 0.18 um CMOS process. The modulation frequency is 100 MHz. The least significant bit width is 78 ps. The chip size is 979×600 〖um〗^2. The total power consumption is 20 mW and the power consumption without output buffer is 2 mW. The measureable PWM duty cycle is 3% ~ 96%. The INL is measured to be -1.08 ~ 1.28 LSB while the DNL is measured to be -0.48 ~ 0.73 LSB.