具簡潔類比型實現暫態時間最佳化導通時間控制之定導通時間降壓型轉換器

Abstract

本篇論文提出應用於定導通時間降壓型轉換器之類比型時間最佳化導通時間控制，此類比型時間最佳化導通時間控制可以快速反應像是中央處理器或是圖形處理器等抽載變化，且此控制方式為第一個將最佳化時間控制應用於定導通時間降壓型轉換器，也因為是在定導通時間降壓型轉換器上做延伸與改善，改善了先前相關論文的一些缺點，包括可以達到良好的輕載效率，低的靜態消耗電流，還有導出的式子跟功率級電感電容沒有相關性，意味著元件誤差不會影響所提出的類比型時間最佳化導通時間控制的實現。另一方面，寄生二極體控制被提出且可以有效的減少快速降載時的輸出電壓突波，只需使用一簡單邏輯閘即可實現。上述所提出之控制方式使用台積電0.18um CMOS製成實現，晶片面積為1.423平方毫米，提出之類比型時間最佳化導通時間控制只佔了0.054平方毫米。從模擬波型來看，類比型時間最佳化導通時間控制降低抽載時所造成的輸出突波電壓51.3%，而寄生二極體控制改善了降載時的輸出突波電壓55.5%。實測波型也顯示了當使用類比型時間最佳化導通時間控制時，輸出突波電壓有52.4%的改善。

A constant on-time buck converter with analog time-optimized on-time control (OTC) is proposed in this thesis to achieve fast load-current step-up transient response for high slew-rate loads such as Central Processing Unit (CPU) and Graphics Processing Unit (GPU). The proposed control firstly implements a constant on-time converter embedded with time-optimized control and solves the prior art issues such as poor light-load efficiency, high quiescent current, and the dependence on the power stage parameters of time-optimized control implying that the mismatched doesn’t affect the proposed OTC . The body diode control (BDC), which minimizes overshoot with simple logic and capacitor-current sensor, is proposed for load current step-down. The proposed control was implemented into an integrated circuit (IC) using 0.18um CMOS process with a chip area of 1.423mm2, where OTC only occupies 0.054mm2. The simulation results show 51.3% and 55.5% reductions of voltage deviation after enabling proposed control functions at load step-up and step-down, respectively. Measurement results show that the undershoot of output voltage improves 52.4% after enabling OTC for a 0.84A load step-up.