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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/71712完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳景然(Ching-Jan Chen) | |
| dc.contributor.author | Yu-Chen Li | en |
| dc.contributor.author | 李育臣 | zh_TW |
| dc.date.accessioned | 2021-06-17T06:07:23Z | - |
| dc.date.available | 2020-01-08 | |
| dc.date.copyright | 2019-01-08 | |
| dc.date.issued | 2019 | |
| dc.date.submitted | 2019-01-07 | |
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Oliver, O. Garcia, J. A. Cobos, “Advanced Control for Very Fast DC-DC Converters Based on Hysteresis of the Cout Current,” IEEE Trans. on Circuits and Systems, Vol. 60, no. 4, Apr 2013. [36] M. Bazes, “Two novel fully complementary self-biased CMOS differential amplifiers,” IEEE J. Solid-State Circuits, Vol. 26, no. 2, pp. 165-168, Feb. 1991. [37] Tony Carusone, David Johns and Kenneth Martin, ”Analog Integrated Circuit Design”, John Wiley & Sons, New York, 2nd edition, 2012. [38] Z. Qiao, X. Zhou, and Q. Li, “A 250mV 77dB DR 10kHz BW SC Delta-Sigma Modulator Exploiting Subthreshold OTAs,” in ESSCIRC, Sep. 2014. [39] J.-M. Liu, P.-Y. Wang, and T.-H. Kuo, “A current-mode DC-DC buck converter with efficiency-optimized frequency control and reconfigurable compensation,” IEEE Trans. Power Electron., Vol. 27, no. 2, pp. 869-880, Feb. 2012. [40] L. Cheng, Y. Liu, and W.-H. Ki, “A 10/30 MHz fast reference-tracking buck converter with DDA-based type-III compensator,” IEEE J. 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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/71712 | - |
| dc.description.abstract | 本篇論文提出應用於定導通時間降壓型轉換器之類比型時間最佳化導通時間控制,此類比型時間最佳化導通時間控制可以快速反應像是中央處理器或是圖形處理器等抽載變化,且此控制方式為第一個將最佳化時間控制應用於定導通時間降壓型轉換器,也因為是在定導通時間降壓型轉換器上做延伸與改善,改善了先前相關論文的一些缺點,包括可以達到良好的輕載效率,低的靜態消耗電流,還有導出的式子跟功率級電感電容沒有相關性,意味著元件誤差不會影響所提出的類比型時間最佳化導通時間控制的實現。另一方面,寄生二極體控制被提出且可以有效的減少快速降載時的輸出電壓突波,只需使用一簡單邏輯閘即可實現。上述所提出之控制方式使用台積電0.18um CMOS製成實現,晶片面積為1.423平方毫米,提出之類比型時間最佳化導通時間控制只佔了0.054平方毫米。從模擬波型來看,類比型時間最佳化導通時間控制降低抽載時所造成的輸出突波電壓51.3%,而寄生二極體控制改善了降載時的輸出突波電壓55.5%。實測波型也顯示了當使用類比型時間最佳化導通時間控制時,輸出突波電壓有52.4%的改善。 | zh_TW |
| dc.description.abstract | A constant on-time buck converter with analog time-optimized on-time control (OTC) is proposed in this thesis to achieve fast load-current step-up transient response for high slew-rate loads such as Central Processing Unit (CPU) and Graphics Processing Unit (GPU). The proposed control firstly implements a constant on-time converter embedded with time-optimized control and solves the prior art issues such as poor light-load efficiency, high quiescent current, and the dependence on the power stage parameters of time-optimized control implying that the mismatched doesn’t affect the proposed OTC . The body diode control (BDC), which minimizes overshoot with simple logic and capacitor-current sensor, is proposed for load current step-down. The proposed control was implemented into an integrated circuit (IC) using 0.18um CMOS process with a chip area of 1.423mm2, where OTC only occupies 0.054mm2. The simulation results show 51.3% and 55.5% reductions of voltage deviation after enabling proposed control functions at load step-up and step-down, respectively. Measurement results show that the undershoot of output voltage improves 52.4% after enabling OTC for a 0.84A load step-up. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-17T06:07:23Z (GMT). No. of bitstreams: 1 ntu-108-R05921017-1.pdf: 3478919 bytes, checksum: 6a0b6e4d870949096acd40079c3749eb (MD5) Previous issue date: 2019 | en |
| dc.description.tableofcontents | 摘要 i
Abstract ii Contents iii List of Figures v List of Tables vii Chapter 1 Introduction 1 1.1 Background: Voltage Regulators (VRs) for Computer Applications 1 1.1 Motivation 4 1.2 Thesis Outline 5 Chapter 2 Constant On-time Buck Converter with Time-optimized Control --- A Review 7 2.1 Constant On-time Control 7 2.1.1 Introduction of Constant On-time Control 7 2.1.2 Stability Analysis of Ripple-based Constant On-time Control 8 2.1.3 Issues of Constant On-time Control with Adding Ramps 11 2.2 Time-optimized Control on Buck Converter 13 2.2.2 Review of Time-optimized Control 13 Chapter 3 Proposed Control for Constant On-time Buck Converter 17 3.1 Circuit Diagram of Constant On-time Buck Converter with the Proposed Controls 17 3.2 Time-optimized On-time Control (OTC) for Load Current Step-up 19 3.3 Body Diode Control for Load Current Step-down 23 3.4 State Diagram and Detection Mechanism 25 Chapter 4 Circuit Implementation 29 4.1 Implementation of Time-optimized On-time Control (OTC) 29 4.2 Capacitor-current Sensor 33 4.3 Current-type Adder 42 4.4 High Speed Three Stages Comparator 43 Chapter 5 Simulation and Measurement Results 49 5.1 Introduction 49 5.2 Printed Circuit Board (PCB) Design and Measurement Setup 54 5.3 Simulation and Measurement Results 56 Chapter 6 Conclusions and Future Works 63 6.1 Conclusions 63 6.2 Future Works 64 Reference 65 | |
| dc.language.iso | en | |
| dc.subject | 降壓型轉換器 | zh_TW |
| dc.subject | 定導通時間控制 | zh_TW |
| dc.subject | 暫態抽載響應 | zh_TW |
| dc.subject | 暫態最佳化導通時間控制 | zh_TW |
| dc.subject | buck converter | en |
| dc.subject | constant on-time control | en |
| dc.subject | load transient response | en |
| dc.subject | time-optimized on-time control | en |
| dc.title | 具簡潔類比型實現暫態時間最佳化導通時間控制之定導通時間降壓型轉換器 | zh_TW |
| dc.title | A Constant On-Time Buck Converter with Compact Analog Time-Optimized On-Time Control | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 107-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 陳德玉(Dan Chen),劉深淵(Shen-Iuan Liu) | |
| dc.subject.keyword | 降壓型轉換器,定導通時間控制,暫態抽載響應,暫態最佳化導通時間控制, | zh_TW |
| dc.subject.keyword | buck converter,constant on-time control,load transient response,time-optimized on-time control, | en |
| dc.relation.page | 70 | |
| dc.identifier.doi | 10.6342/NTU201900024 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2019-01-07 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
| 顯示於系所單位: | 電機工程學系 | |
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|---|---|---|---|
| ntu-108-1.pdf 未授權公開取用 | 3.4 MB | Adobe PDF |
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