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  1. NTU Theses and Dissertations Repository
  2. 電機資訊學院
  3. 電機工程學系
請用此 Handle URI 來引用此文件: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/71712
完整後設資料紀錄
DC 欄位值語言
dc.contributor.advisor陳景然(Ching-Jan Chen)
dc.contributor.authorYu-Chen Lien
dc.contributor.author李育臣zh_TW
dc.date.accessioned2021-06-17T06:07:23Z-
dc.date.available2020-01-08
dc.date.copyright2019-01-08
dc.date.issued2019
dc.date.submitted2019-01-07
dc.identifier.citation[1] F. C. Lee, P. Barbosa, P. Xu, J. Zhang, B. Yang, and F. Canales “Topologies and design considerations for distributed power system applications,” in Proc. IEEE, vol. 89, no. 6, pp. 939-950, 2001.
[2] F. C. Lee, “Power supplies trends – from architecture to building blocks,” presented at National Semiconductor Virtual Laboratories Distinguished Faculty Seminar, 2010. Available at http://www.cpes.vt.edu.
[3] Texas Instrument document, “Power solutions for Intel IMVP6.5 platform” Available at http://focus.ti.com/docs/solution/folders/print/563.html.
[4] B. Lee, M. K. Song, A. Maity, D. Brian M, “10.7 A 25MHz 4-phase SAW hysteretic DC-DC converter with 1-cycle APC achieving 190ns tsettle to 4A load transient and above 80% efficiency in 96.7% of the power range,” in IEEE ISSCC, Mar. 2017.
[5] C. Song, “Accuracy analysis of constant-on time current-mode dc-dc converters for powering microprocessors,” in Proc. IEEE APEC, 2009, pp. 97-101.
[6] R. Redl and J. Sun, “Ripple-based control of switching regulators – An overview,” IEEE Trans. Power Electron., vol.24, no. 12, pp. 2669-2280, Dec. 2009.
[7] J. Sun, “Characterization and performance comparison of ripple based control for voltage regulators modules,” IEEE Trans. Power Electron., vol.21, no. 2, pp. 346-353, Mar. 2006.
[8] J. Li and F. C. Lee, “Modeling of V2 current-mode control,” in Proc. IEEE APEC, 2009, pp. 298-304.
[9] S. Qu, “Modeling and design considerations of V2 controlled buck regulator,” in Proc. IEEE APEC, 2001, pp. 507-513.
[10] Y.-J. Chen, D. Chen, Y.-C. Lin, and C.-J. Chen “A novel constant on-time current-mode control scheme to achieve adaptive voltage positioning for DC power converters,” in Proc. IEEE IECON 2012, pp. 104-109.
[11] K. Yao, Y. Ren, J. Sun, K. Lee, M. Xu, J. Zhou and F. C, Lee, “Adaptive voltage position design for voltage regulators,” in Proc. IEEE APEC, 2004, pp. 272-278.
[12] C. Song and J. L. Nilles, “Multiple-phase high-accuracy hysteretic current-mode voltage regulator for powering micorprocessors,” in Proc. IEEE APEC, 2008, pp. 517-522.
[13] W. Huang, D. Clavette, G. Schuellein, M. Crowther and J. Wallace, “System accuracy analysis of the multiphase voltage regulator module,” IEEE Trans. Power Electron., vol.22, no. 3, pp. 1019-1026, May 2007.
[14] F. Yu, F. C. Lee, and P. Mattavelli “A small-signal model for V¬2 control with composite output capacitors based on describing function approach,” in Proc. IEEE ECCE, 2011, pp. 1236-1243.
[15] Y. Lee, S. Wang, and K. Chen, “Quadratic differential and integration technique in V2 control buck converter with small ESR capacitors,” IEEE Trans. Power Electron., vol.25, no. 4, pp. 829-838, Apr. 2010.
[16] C. C. Fang and R. Redl, “Subharmonic stability limits for the buck converter with ripple-based constant on-time control and feedback filter,” IEEE Trans. Power Electron., vol.29, no. 4, pp. 2135-2142, Apr. 2013.
[17] T. Qian and W. Wu, “Analysis of the ramp compensation approaches to improve stability for buck converters with constant-on-time control,” IET Power Electronics, vol.5, issue. 2, 2012, pp. 196-204.
[18] T. Qian, “Subharmonic analysis for buck converters with constant.on-time control and ramp compensation,” IEEE Trans. Industrial Electron., vol. 60, no. 5, pp. 1780-1786, May, 2013.
[19] S. Tian, F. C. Lee, Q. Li and Y. Yan, “Unified equivalent circuit model of V2 control,” in Proc. IEEE APEC, 2014, pp. 1016-1023.
[20] M. Lee, D. Chen, K. Huang, C. W. Liu and B. Tai, “Modeling and design for a novel adaptive voltage positioning (AVP) scheme for multiphase VRMs,” IEEE Trans. Power Electron., vol. 23, no. 4, pp. 1733-1742, Jul. 2008.
[21] C. Chen, D. Chen, C. Tseng, Y. Chang and K. Wang, “A novel ripple-based constant on-time control with virtual inductor current ripple for buck converter with ceramic output capacitors,” in Proc. IEEE APEC, 2011, pp. 1488-1493.
[22] Y. C. Lin, C. J. Chen, D. Chen, B. Wang, “A ripple-based constant on-time control with virtual inductor current and offset cancellation for DC power converter,” IEEE Trans. Power Electron., Vol. 27, no. 10, pp 4301-4310, Oct. 2012.
[23] K. Cheng, F. C. Lee, and P. Mattavelli,“Adaptive ripple-based constant on-time control with internal ramp compensations for buck converter,' in Proc. IEEE APEC, 2014, pp. 440-446.
[24] Texas Instruments, Single Phase D-CAP+TM Mode Step Down Controller for
IMVP6+ CPU/GPU Vcore TPS51610 Datasheet. (2009) [online] http://www.ti.com/product/tps51610
[25] S. Tian, K. -Y. Cheng, F. C. Lee, and P. Mattavelli, “Small-signal model analysis and design of constant on-time V2 control for low-ESR caps with external ramp
compensation,' in Proc. IEEE ECCE., 2011, pp.2944-2951.
[26] W. H. Yang, C. J. Huang, H. H. Huang, W. T. Ling, K. H. Chen, Y. H. Lin, S. R. Lin, T. Y. Tsai, “A constant-on-time control DC-DC buck converter with the pseudowave tracking technique for regulation accuracy and load transient enhancement,” IEEE Trans. Power Electron., Vol. 33, no. 7, pp.6187-6198, Jul. 2018.
[27] S. Kapat and P. T. Krein, “Improved time optimal control of a buck converter based on capacitor current,” IEEE Trans. Power Electron., Vol. 27, no. 3, pp. 1444–1454, Mar. 2012.
[28] S. H. Chien, T. H. Hung, S. Y. Huang, T.-H. Kuo, “A monolithic capacitor-current-controlled hysteretic buck converter with time-optimized feedback circuit,” IEEE J. Solid-State Circuits, Vol. 50, no. 11, pp.2524-2532, Nov. 2015.
[29] S.-Y. Huang, K.-Y. Fang, Y.-W. Huang, S.-H. Chien, T.-H. Kuo, “Capacitor-current-sensor calibration technique and application in a 4-Phase buck converter with load-time optimization,” in IEEE ISSCC, Feb. 2016, pp.228-229.
[30] Y. W. Huang, T.-H. Kuo, S. Y. Huang, and K. Y. Fang, “A Four-Phase Buck Converter With Capacitor-current–sensor Calibration for Load-Time-Response Optimization That Reduces Undershoot/Overshoot and Shortens Settling Time to Near Their Theoretical Limits,” IEEE J. Solid-State Circuits, Vol. 53, no. 2, pp. 552-568, Feb. 2018.
[31] G. Feng, E. Meyer, Y.-F. Liu, “A New Digital Control Algorithm to Achieve Optimal Dynamic Performance in DC-to-DC Converters,” IEEE Trans. Power Electron., Vol. 22, no. 4, pp.1489-1498, Jul. 2007.
[32] E. Meyer, Z. Zhang, Y.-F. Liu, “An optimal control method for buck converters using a practical capacitor charge balance technique,” IEEE Trans. Power Electron., Vol. 23, no. 4, pp.1802-1812, Jul. 2008
[33] S. C. Huerta, P. Alou, J. A. Oliver, O. Garcia, J. A. Cobos, and A. Abou-Alfotouh, “Design methodology of a non-invasive sensor to measure the current of output capacitor for a very fast non-linear control,” in Proc. IEEE Appl. Power Electron. Conf., 2009, pp. 806-811.
[34] S. C. Huerta, P. Alou, J. A. Oliver, O. Garcia, J. A. Cobos, and A. Abou-Alfotouh, “Non-linear control for DC-DC converters based on hysteresis of the COUT current with a frequency loop to operate at constant frequency,” IEEE Trans. Industrial Electron., Vol. 58, no. 3, pp. 1036–1043, Mar. 2011.
[35] S. C. Huerta, A. Soto, P. Alou, J. A. Oliver, O. Garcia, J. A. Cobos, “Advanced Control for Very Fast DC-DC Converters Based on Hysteresis of the Cout Current,” IEEE Trans. on Circuits and Systems, Vol. 60, no. 4, Apr 2013.
[36] M. Bazes, “Two novel fully complementary self-biased CMOS differential amplifiers,” IEEE J. Solid-State Circuits, Vol. 26, no. 2, pp. 165-168, Feb. 1991.
[37] Tony Carusone, David Johns and Kenneth Martin, ”Analog Integrated Circuit Design”, John Wiley & Sons, New York, 2nd edition, 2012.
[38] Z. Qiao, X. Zhou, and Q. Li, “A 250mV 77dB DR 10kHz BW SC Delta-Sigma Modulator Exploiting Subthreshold OTAs,” in ESSCIRC, Sep. 2014.
[39] J.-M. Liu, P.-Y. Wang, and T.-H. Kuo, “A current-mode DC-DC buck converter with efficiency-optimized frequency control and reconfigurable compensation,” IEEE Trans. Power Electron., Vol. 27, no. 2, pp. 869-880, Feb. 2012.
[40] L. Cheng, Y. Liu, and W.-H. Ki, “A 10/30 MHz fast reference-tracking buck converter with DDA-based type-III compensator,” IEEE J. Solid-State Circuits, Vol.49, no. 12, pp.2788-2799, Dec. 2014.
[41] K.-I Wu, B.-T Hwang, and C.C-P. Chen, “Synchronous double-pumping technique for integrated current-mode PWM DC-DC converters demand on fast-transient response,” IEEE Trans. Power Electron., Vol. 32, no. 1, pp. 849-865, Jan. 2017.
[42] D. -H. Jung, K. Kim, S. Joo, and S.-O. Jung, “0.293-mm2 fast transient response hysteretic quasi-V2 DC-DC Converter with area-efficient time-domain-based controller in 0.35-μm CMOS,” IEEE J. Solid-State Circuits, Vol.53, no. 6, pp.1844-1855, Jun. 2018.
dc.identifier.urihttp://tdr.lib.ntu.edu.tw/jspui/handle/123456789/71712-
dc.description.abstract本篇論文提出應用於定導通時間降壓型轉換器之類比型時間最佳化導通時間控制,此類比型時間最佳化導通時間控制可以快速反應像是中央處理器或是圖形處理器等抽載變化,且此控制方式為第一個將最佳化時間控制應用於定導通時間降壓型轉換器,也因為是在定導通時間降壓型轉換器上做延伸與改善,改善了先前相關論文的一些缺點,包括可以達到良好的輕載效率,低的靜態消耗電流,還有導出的式子跟功率級電感電容沒有相關性,意味著元件誤差不會影響所提出的類比型時間最佳化導通時間控制的實現。另一方面,寄生二極體控制被提出且可以有效的減少快速降載時的輸出電壓突波,只需使用一簡單邏輯閘即可實現。上述所提出之控制方式使用台積電0.18um CMOS製成實現,晶片面積為1.423平方毫米,提出之類比型時間最佳化導通時間控制只佔了0.054平方毫米。從模擬波型來看,類比型時間最佳化導通時間控制降低抽載時所造成的輸出突波電壓51.3%,而寄生二極體控制改善了降載時的輸出突波電壓55.5%。實測波型也顯示了當使用類比型時間最佳化導通時間控制時,輸出突波電壓有52.4%的改善。zh_TW
dc.description.abstractA constant on-time buck converter with analog time-optimized on-time control (OTC) is proposed in this thesis to achieve fast load-current step-up transient response for high slew-rate loads such as Central Processing Unit (CPU) and Graphics Processing Unit (GPU). The proposed control firstly implements a constant on-time converter embedded with time-optimized control and solves the prior art issues such as poor light-load efficiency, high quiescent current, and the dependence on the power stage parameters of time-optimized control implying that the mismatched doesn’t affect the proposed OTC . The body diode control (BDC), which minimizes overshoot with simple logic and capacitor-current sensor, is proposed for load current step-down. The proposed control was implemented into an integrated circuit (IC) using 0.18um CMOS process with a chip area of 1.423mm2, where OTC only occupies 0.054mm2. The simulation results show 51.3% and 55.5% reductions of voltage deviation after enabling proposed control functions at load step-up and step-down, respectively. Measurement results show that the undershoot of output voltage improves 52.4% after enabling OTC for a 0.84A load step-up.en
dc.description.provenanceMade available in DSpace on 2021-06-17T06:07:23Z (GMT). No. of bitstreams: 1
ntu-108-R05921017-1.pdf: 3478919 bytes, checksum: 6a0b6e4d870949096acd40079c3749eb (MD5)
Previous issue date: 2019
en
dc.description.tableofcontents摘要 i
Abstract ii
Contents iii
List of Figures v
List of Tables vii
Chapter 1 Introduction 1
1.1 Background: Voltage Regulators (VRs) for Computer Applications 1
1.1 Motivation 4
1.2 Thesis Outline 5
Chapter 2 Constant On-time Buck Converter with Time-optimized Control --- A Review 7
2.1 Constant On-time Control 7
2.1.1 Introduction of Constant On-time Control 7
2.1.2 Stability Analysis of Ripple-based Constant On-time Control 8
2.1.3 Issues of Constant On-time Control with Adding Ramps 11
2.2 Time-optimized Control on Buck Converter 13
2.2.2 Review of Time-optimized Control 13
Chapter 3 Proposed Control for Constant On-time Buck Converter 17
3.1 Circuit Diagram of Constant On-time Buck Converter with the Proposed Controls 17
3.2 Time-optimized On-time Control (OTC) for Load Current Step-up 19
3.3 Body Diode Control for Load Current Step-down 23
3.4 State Diagram and Detection Mechanism 25
Chapter 4 Circuit Implementation 29
4.1 Implementation of Time-optimized On-time Control (OTC) 29
4.2 Capacitor-current Sensor 33
4.3 Current-type Adder 42
4.4 High Speed Three Stages Comparator 43
Chapter 5 Simulation and Measurement Results 49
5.1 Introduction 49
5.2 Printed Circuit Board (PCB) Design and Measurement Setup 54
5.3 Simulation and Measurement Results 56
Chapter 6 Conclusions and Future Works 63
6.1 Conclusions 63
6.2 Future Works 64
Reference 65
dc.language.isoen
dc.subject降壓型轉換器zh_TW
dc.subject定導通時間控制zh_TW
dc.subject暫態抽載響應zh_TW
dc.subject暫態最佳化導通時間控制zh_TW
dc.subjectbuck converteren
dc.subjectconstant on-time controlen
dc.subjectload transient responseen
dc.subjecttime-optimized on-time controlen
dc.title具簡潔類比型實現暫態時間最佳化導通時間控制之定導通時間降壓型轉換器zh_TW
dc.titleA Constant On-Time Buck Converter with Compact Analog Time-Optimized On-Time Controlen
dc.typeThesis
dc.date.schoolyear107-1
dc.description.degree碩士
dc.contributor.oralexamcommittee陳德玉(Dan Chen),劉深淵(Shen-Iuan Liu)
dc.subject.keyword降壓型轉換器,定導通時間控制,暫態抽載響應,暫態最佳化導通時間控制,zh_TW
dc.subject.keywordbuck converter,constant on-time control,load transient response,time-optimized on-time control,en
dc.relation.page70
dc.identifier.doi10.6342/NTU201900024
dc.rights.note有償授權
dc.date.accepted2019-01-07
dc.contributor.author-college電機資訊學院zh_TW
dc.contributor.author-dept電機工程學研究所zh_TW
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