0.13 µm CMOS 內插升頻式數位類比轉換器

Abstract

本論文主旨為實現一具備四倍內插升頻之數位類比轉換器，為了讓數位類比轉換器能夠操作在高速，本論文所採之架構為電流引導式之數位類比轉換器，在訊號輸入數位類比轉換器前，將先經過一具有升頻功能之數位合成的內插升頻電路，不僅可以增加輸出結果的取樣點數，讓電壓輸出波型更加柔和，更能利用內插的特性在以取樣頻率為中心點的兩端產生輸入頻率之諧波，進而達到將所輸入之頻譜升頻至取樣頻率的功能。最後在佈局圖的部分利用分散電流源的方式來減少電流源的不匹配效應(Mismatch)。

在晶片實現上，均使用0.13微米CMOS實現電路，整體晶片面積為0.9 × 0.9 〖mm〗^2，其中電流源電路的面積為 0.584 × 0.665 〖mm〗^2，並在電源電壓1.2 V下達到差動輸出擺幅為0.8 V的數位類比轉換器，根據量測結果，INL/DNL皆小於0.3 LSB，SFDR約為38 dB左右，而總功率消耗約為23 mW。在AFDPWM訊號應用方面，量測K值為3，PWM頻率為15 MHz，頻寬為3MHz的狀況下，ACLR量測出來的結果為-29.2 dBc，將訊號載波至中心頻為40 MHz時，ACLR則為 -28.9 dBc左右。

The purpose of this thesis is to implement a digital-to-analog converter with four times up-sampling technique by using interpolation. To make the digital-to-analog converter operate in high frequency, the architecture adopted is current-steering method. Before the input signal goes into the digital-to-analog converter, it will first pass through the digital-synthesis circuit with interpolative up-sampling function. This interpolative up-sampling circuit not only improves the linearity of the output, but also generates harmonics centered at the up-sampling carrier frequency and make the input signal up-sampled to the carrier frequency by its interpolative characteristic, which is the main goal of this thesis. In the layout part, this thesis splits the current source placement to reduce the mismatch of the current sources. The chip designed in this thesis is implemented in 0.13μm CMOS process. The chip size is 0.9×0.9 m'm' ^'2' and the size of current source part is 0.584×0.665 m'm' ^'2' . The output swing is 0.8 V by using 1.2 V supply voltage. The measured DNL/INL are both less than 0.3 LSB, SFDR is 38 dB with 10 MHz sine wave and the total power consumption is 23 mW. In the AFDPWM (aliasing-free digital pulse width modulation ) application , the measured ACLR is -29.2 dBc when K factor is 3, frequency of PWM is 15 MHz and the bandwidth is 3 MHz, and the measured ACLR is -28.9 dBc when the signal is up-convert to 40 MHz.