考慮汲極結構相鄰之多重排高標準元件擺置

Abstract

隨著製程技術的縮小，汲極結構相鄰限制在現代電路設計中產生了新的挑戰，這也對最新製程中多重排高標準元件擺置帶來了額外的困難。在這篇論文裡，我們提出文獻上第一個考慮汲極結構相鄰限制的多重排高擺置問題，整個流程從處理完全域擺置一直到細部擺置。我們提出的演算法主要包含三大步驟 : (1) 考慮汲極結構相鄰限制的前處理。 (2) 合理化。以及 (3) 考慮汲極結構相鄰限制的細部擺置。首先，在前處理階段，我們考慮源極與汲極的每行分布比例，將標準元件放入最理想的行內。接著，在合理化階段，我們延伸文獻上已存在的模組矩陣分割疊代方法，依照每行已決定好的標準結構之排序下，移除，在達到全部標準元件總位移最小化的目標下，消除標準元件重疊的問題。最後，在細部擺置階段，我們以布林可滿足問題為基礎提出一個方法，可以同時考慮整個電路擺置下進行翻轉標準元件與交換相鄰的標準元件。實驗結果顯示，對比於現有文獻的最小路徑方法，我們提出的演算法在合理的運行時間內以最小的位移來有效解決汲極結構相鄰違規。

Along with device scaling, the drain-to-drain abutment (DDA) constraint arises as an emerging challenge in modern circuit designs, which incurs additional difficulties especially for designs with mixed-cell-height standard cells which have prevailed in advanced technology. This thesis presents the first work to address the mixed-cell-height placement problem considering the DDA constraint from post global placement throughout detailed placement. Our algorithms consists of three major stages: (1) DDA-aware preprocessing, (2) legalization, and (3) DDA-aware detailed placement. In the DDA-aware preprocessing stage, we first align cells to desired rows, considering the distribution ratio of source nodes to drain nodes. After deciding the cell ordering of every row, we adopt the modulus-based matrix splitting iteration method to remove all cell overlaps with minimum total displacement in the legalization stage. For detailed placement, we propose a satisfiability-based approach which considers the whole layout to flip a subset of cells and swap pairs of adjacent cells simultaneously. Compared with a shortest-path method, experimental results show that our proposed algorithm can significantly reduce cell violations and displacements with reasonable runtime.