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  1. NTU Theses and Dissertations Repository
  2. 工學院
  3. 材料科學與工程學系
請用此 Handle URI 來引用此文件: http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/70617
完整後設資料紀錄
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dc.contributor.advisor陳敏璋
dc.contributor.authorTsung-Han Shenen
dc.contributor.author沈宗翰zh_TW
dc.date.accessioned2021-06-17T04:32:43Z-
dc.date.available2023-08-14
dc.date.copyright2018-08-14
dc.date.issued2018
dc.date.submitted2018-08-10
dc.identifier.citation參考文獻
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19. Fang, Q.; Hodson, C.; Xu, C.; Gunn, R., Nucleation and Growth of Platinum Films on High-k/Metal Gate Materials by Remote Plasma and Thermal ALD. Physics Procedia 2012, 32, 551-560.
20. Onishi, K.; Chang Seok, K.; Rino, C.; Hag-Ju, C.; Gopalan, S.; Nieh, R. E.; Krishnan, S. A.; Lee, J. C., Improvement of surface carrier mobility of HfO2 MOSFETs by high-temperature forming gas annealing. IEEE Transactions on Electron Devices 2003, 50 (2), 384-390.
21. An, J.; Usui, T.; Logar, M.; Park, J.; Thian, D.; Kim, S.; Kim, K.; Prinz, F. B., Plasma Processing for Crystallization and Densification of Atomic Layer Deposition BaTiO3 Thin Films. ACS Applied Materials & Interfaces 2014, 6 (13), 10656-10660.
22. Li, K. S.; Chen, P. G.; Lai, T. Y.; Lin, C. H.; Cheng, C. C.; Chen, C. C.; Wei, Y. J.; Hou, Y. F.; Liao, M. H.; Lee, M. H.; Chen, M. C.; Sheih, J. M.; Yeh, W. K.; Yang, F. L.; Salahuddin, S.; Hu, C. In Sub-60mV-swing negative-capacitance FinFET without hysteresis, 2015 IEEE International Electron Devices Meeting (IEDM), 7-9 Dec. 2015; 2015; pp 22.6.1-22.6.4.
23. Khan, A. I.; Chatterjee, K.; Duarte, J. P.; Lu, Z.; Sachid, A.; Khandelwal, S.; Ramesh, R.; Hu, C.; Salahuddin, S., Negative Capacitance in Short-Channel FinFETs Externally Connected to an Epitaxial Ferroelectric Capacitor. IEEE Electron Device Letters 2016, 37 (1), 111-114.
24. Salvatore, G. A.; Rusu, A.; Ionescu, A. M., Experimental confirmation of temperature dependent negative capacitance in ferroelectric field effect transistor. Applied Physics Letters 2012, 100 (16), 163504.
25. Lin, C. I.; Khan, A. I.; Salahuddin, S.; Hu, C., Effects of the Variation of Ferroelectric Properties on Negative Capacitance FET Characteristics. IEEE Transactions on Electron Devices 2016, 63 (5), 2197-2199.
26. Lee, M. H.; Fan, S. T.; Tang, C. H.; Chen, P. G.; Chou, Y. C.; Chen, H. H.; Kuo, J. Y.; Xie, M. J.; Liu, S. N.; Liao, M. H.; Jong, C. A.; Li, K. S.; Chen, M. C.; Liu, C. W. In Physical thickness 1.x nm ferroelectric HfZrOx negative capacitance FETs, 2016 IEEE International Electron Devices Meeting (IEDM), 3-7 Dec. 2016; 2016; pp 12.1.1-12.1.4.
27. Jo, J.; Shin, C., Negative Capacitance Field Effect Transistor With Hysteresis-Free Sub-60-mV/Decade Switching. IEEE Electron Device Letters 2016, 37 (3), 245-248.
28. Zhirnov, V. V.; Cavin, R. K., Negative capacitance to the rescue? Nature Nanotechnology 2008, 3, 77.
29. Salahuddin, S.; Datta, S., Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices. Nano Letters 2008, 8 (2), 405-410.
30. Appleby, D. J. R.; Ponon, N. K.; Kwa, K. S. K.; Zou, B.; Petrov, P. K.; Wang, T.; Alford, N. M.; O’Neill, A., Experimental Observation of Negative Capacitance in Ferroelectrics at Room Temperature. Nano Letters 2014, 14 (7), 3864-3868.
31. Khan, A. I.; Bhowmik, D.; Yu, P.; Kim, S. J.; Pan, X.; Ramesh, R.; Salahuddin, S., Experimental evidence of ferroelectric negative capacitance in nanoscale heterostructures. Applied Physics Letters 2011, 99 (11), 113501.
32. Müller, J.; Yurchuk, E.; Schlösser, T.; Paul, J.; Hoffmann, R.; Müller, S.; Martin, D.; Slesazeck, S.; Polakowski, P.; Sundqvist, J.; Czernohorsky, M.; Seidel, K.; Kücher, P.; Boschke, R.; Trentzsch, M.; Gebauer, K.; Schröder, U.; Mikolajick, T. In Ferroelectricity in HfO2 enables nonvolatile data storage in 28 nm HKMG, 2012 Symposium on VLSI Technology (VLSIT), 12-14 June 2012; 2012; pp 25-26.
33. Tomida, K.; Kita, K.; Toriumi, A., Dielectric constant enhancement due to Si incorporation into HfO2. Applied Physics Letters 2006, 89 (14), 142902.
34. Böscke, T. S.; Müller, J.; Bräuhaus, D.; Schröder, U.; Böttger, U., Ferroelectricity in hafnium oxide thin films. Applied Physics Letters 2011, 99 (10), 102903.
35. Müller, J.; Böscke, T. S.; Bräuhaus, D.; Schröder, U.; Böttger, U.; Sundqvist, J.; Kücher, P.; Mikolajick, T.; Frey, L., Ferroelectric Zr0.5Hf0.5O2 thin films for nonvolatile memory applications. Applied Physics Letters 2011, 99 (11), 112901.
36. Park, M. H.; Kim, H. J.; Kim, Y. J.; Lee, W.; Kim, H. K.; Hwang, C. S., Effect of forming gas annealing on the ferroelectric properties of Hf0.5Zr0.5O2 thin films with and without Pt electrodes. Applied Physics Letters 2013, 102 (11), 112914.
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39. Lin, B.-T.; Lu, Y.-W.; Shieh, J.; Chen, M.-J., Induction of ferroelectricity in nanoscale ZrO2 thin films on Pt electrode without post-annealing. Journal of the European Ceramic Society 2017, 37 (3), 1135-1139.
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dc.identifier.urihttp://tdr.lib.ntu.edu.tw/jspui/handle/123456789/70617-
dc.description.abstract本論文主要分為兩個部分,第一部分在介紹電漿處理對薄膜的影響。在原子層沉積(Atomic layer deposition)製程中加入電漿處理後,發現薄膜厚度有被抑制的效果。而經電漿處理後的薄膜,其金氧半電容元件比一般ALD製程,也有較佳的電性表現。第二部分為鐵電負電容效應的研究。我們使用電漿增強型原子層沉積技術製作氧化薄膜,可以得到具有鐵電性的材料。而氧化物薄膜會因為其厚度增加而有較低的殘留極化值,可能由於內部有非鐵電相的存在。以此鐵電材料堆疊於順電材料上時,可發現電容放大的效應。zh_TW
dc.description.abstractThis paper is divided into two parts. The first part investigates the effect of plasma treatment on the film prepared by the atomic layer deposition (ALD). When the plasma treatment was introduced to the ALD process, it was found that the film thickness was suppressed. The plasma-treated metal-oxide-semiconductor capacitors also reveal better electrical performance than that treated by the conventional ALD process. The second part is the study of the negative capacitance effect of ferroelectric thin films. Plasma-enhanced atomic layer deposition was used to prepare ferroelectric thin films. The residual polarization of the ferroelectric oxide thin film decreases with the increasing film thickness, attributed to the presence of a non-ferroelectric phase. The effect of capacitance enhancement can be observed when the ferroelectric thin film is stacked on a paraelectric layer.en
dc.description.provenanceMade available in DSpace on 2021-06-17T04:32:43Z (GMT). No. of bitstreams: 1
ntu-107-R05527046-1.pdf: 3345562 bytes, checksum: 8eb296835c2cae3ea5ad574abba55ab3 (MD5)
Previous issue date: 2018
en
dc.description.tableofcontents致謝 I
摘要 II
Abstract III
目錄 IV
圖目錄 VI
表目錄 VIII
第一章 簡介 1
1.1 原子層沉積技術(ALD) 1
1.1.1 原子層沉積技術 1
1.1.2 電漿增強原子層沉積技術 6
1.2 鐵電材料 10
1.3 論文導覽 13
第二章 電漿處理對薄膜之影響 14
2.1 研究動機 14
2.2 研究簡介 14
2.3 實驗步驟 16
2.4 實驗結果與討論 21
2.4.1 薄膜厚度分析 21
2.4.2 薄膜MOS結構電性分析 27
2.5 結論 31
第三章 鐵電負電容元件之研究 32
3.1 研究動機 32
3.2 研究簡介 32
3.3 實驗步驟 37
3.4 實驗結果與討論 41
3.4.1 順電層材料串聯電容表現 41
3.4.2 氧化物薄膜之鐵電性質量測 43
3.4.3 氧化物薄膜之晶相分析 47
3.4.4 鐵電材料串聯順電材料之電容表現 51
3.4.5 負電容理論模型 55
3.5 結論 60
第四章 總結 61
4.1 參考文獻 62
dc.language.isozh-TW
dc.subject原子層沉積技術zh_TW
dc.subject金氧半電容元件zh_TW
dc.subject負電容zh_TW
dc.subject電漿處理zh_TW
dc.subject鐵電材料zh_TW
dc.subject順電材料zh_TW
dc.subjectplasma treatmenten
dc.subjectAtomic layer depositionen
dc.subjectparaelectric materialen
dc.subjectferroelectric materialen
dc.subjectnegative capacitanceen
dc.title使用電漿增強型原子層沉積技術探討電漿處理及鐵電負電容之研究zh_TW
dc.titleInvestigation of Plasma Treatment and Ferroelectric Negative Capacitance using Plasma Enhanced Atomic Layer Depositionen
dc.typeThesis
dc.date.schoolyear106-2
dc.description.degree碩士
dc.contributor.oralexamcommittee吳肇欣,廖洺漢,李峻霣
dc.subject.keyword原子層沉積技術,金氧半電容元件,電漿處理,順電材料,鐵電材料,負電容,zh_TW
dc.subject.keywordAtomic layer deposition,plasma treatment,paraelectric material,ferroelectric material,negative capacitance,en
dc.relation.page66
dc.identifier.doi10.6342/NTU201802986
dc.rights.note有償授權
dc.date.accepted2018-08-10
dc.contributor.author-college工學院zh_TW
dc.contributor.author-dept材料科學與工程學研究所zh_TW
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