連續時間增量型三角積分調變器

Abstract

增量型三角積分調變器有許多應用，包含生物醫學測量、感測器陣列測量，並適用於任何多通道感測平台，這些物聯網的應用通常結合高速傳輸與無線網路連結的特性，因此低功率消耗是首先要被考慮的。此論文呈獻一個三階五位元連續時間增量型三角積分調變器，為了低功耗的考量，我們使用更有效率的連續漸進式暫存類比數位轉換器取代傳統的快閃式類比數位轉換器並且利用雜訊耦合的技術減少使用消耗功率的運算放大器之數量且達到相同的雜訊成型效果，迴路延遲補償也嵌入在連續漸進式暫存類比數位轉換器而不需要額外的數位類比轉換器。本晶片使用台積電四十奈米互補式金屬氧化物半導體1P6M製程所實現，本晶片操作於一百六十萬取樣頻率，並於二十五千赫茲的有效頻寬下於增量型模式得到71.98 dB的訊號雜訊失真比，於三角積分模式下得到72.34 dB的訊號雜訊失真比。在1.2伏特和1.5伏特的電源供應下總共消耗225微瓦，晶片的核心面積小於0.318平方毫米。

Incremental delta-sigma data converter (IDC) has many useful applications including biomedical measurement and sensor array measurement, and is suitable for multi-channel platforms. This application for internet of things (IOT) always combine the characteristics of high-speed transmission and wireless network connectivity. Therefore, low power consumption is the first to be considered.This thesis presents a 3rd-order, 5-bit continuous-time incremental delta-sigma data converter (CTIDC). For low power consideration, we replace conventional FLASH ADC by power-efficient successive-approximation-register (SAR) ADC and utilizing the noise coupling (NC) technique to reduce the numbers of power-hungry op-amps for the same noise shaping effect. The excess loop delay compensation (ELDC) is also embedded in the SAR ADC without using additional DAC.Fabricated in TSMC 40 nm LP 1P6M technology, the proposed modulator is operated at 1.6MHz sampling clock. It achieves peak SNDR of 71.98 dB in IDC mode and 72.34 dB SNDR in SDM mode within 25 kHz signal bandwidth. This chip dissipates 225 μW from 1.2V/1.5V supply voltage. The active area of this modulator occupies less than 0.318mm2.