一種低功耗多通道連續漸進式類比數位轉換器的設計方法

Abstract

連續漸進式暫存類比數位轉換器(SAR ADC)因為其良好的功耗效率而被廣泛應用於可攜式生醫電路系統。然而，SAR ADC的設計最佳化對許多電路工程師而言往往是非常耗費時間的。本論文提出一種基於電路行為模型的低功耗多通道交錯時序SAR ADC的系統化電路設計方法，目標是能夠輔助工程師評估一套SAR ADC電路規格的可行性。電路行為模型基於程式語言MATLAB，由不匹配模型、延遲模型、雜訊模型組成，行為模型透過Cadence Spectre的電晶體層級模擬來驗證，本文也提供基於一百八十奈米CMOS製程的設計範例以展示此設計方法的準確性。

Successive approximation register analog-to-digital converters (SAR ADCs) are widely used in portable biomedical electronic systems due to their excellent power efficiency. However, the design optimization of SAR ADCs is often very time-consuming for many circuit engineers. This paper proposes a systematic design methodology for low-power time-interleaved SAR ADCs based on circuit behavioral model, aiming to assist engineers to evaluate the feasibility of a given specification of SAR ADC. The circuit behavioral model is based on MATLAB and consisted of mismatch model, delay model and noise model. The behavioral model is verified through transistor-level simulation with Cadence Spectre. Design examples based on 0.18um CMOS technology are also provided to demonstrate the accuracy of this design methodology.