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| ???org.dspace.app.webui.jsptag.ItemTag.dcfield??? | Value | Language |
|---|---|---|
| dc.contributor.advisor | 李泰成(Tai-Cheng Lee) | |
| dc.contributor.author | Kuan-Jung Liao | en |
| dc.contributor.author | 廖冠榮 | zh_TW |
| dc.date.accessioned | 2021-06-17T04:29:22Z | - |
| dc.date.available | 2023-08-14 | |
| dc.date.copyright | 2018-08-14 | |
| dc.date.issued | 2018 | |
| dc.date.submitted | 2018-08-13 | |
| dc.identifier.citation | [1] A. P. Chandrakasan and R. W. Brodersen, “Minimizing power consumption in digital CMOS circuits,” Proc. IEEE, vol. 83, pp. 498–523, Apr. 1995.
[2] B. Razavi, Principles of Data Conversion System Design, Wiley-IEEE Press, New York, 1995. [3] D. Johns and K. Martin, Analog Integrated Circuit Design, John Wiley & Sons, New York, 1997. [4] M. Gustavsson, J. J. Wikner, and N. Tan, CMOS Data Converters for Communi -cations, Kluwer Academic Publisher, Boston, 2000. [5] L. Kull et al., “A 32 mW 8 b 8.8 GS/s SAR ADC with low-power capacitive reference buffers in 32 nm digital SOI CMOS,” Symp. VLSI Circuits Dig. Tech. Papers, pp. 260–261, Jun. 2013. [6] W. Liu, Y. Chang, S.-K. Hsien, B.-W. Chen, Y.-P. Lee, W.-T. Chen, T.-Y. Yang, G.-K. Ma, and Y. Chiu, “A 600MS/s 30mW 0.13μm CMOS ADC Array Achieving Over 60dB SFDR with Adaptive Digital Equalization,” IEEE ISSCC. Dig. Tech. Papers, pp. 82–83, Feb. 2009. [7] B. P. Ginsburg and A. P. Chandrakasan, “500-MS/s 5-bit ADC in 65-nm CMOS with Split Capacitor Array DAC,” IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. 739–747, Apr. 2007. [8] S. Haenzsche, S. Henker, and R. Schuffny, “Modelling of Capacitor Mismatch and Non-linearity Effects in Charge Redistribution SAR ADCs,” Proc. MIXDES, pp. 300-305, Jun. 2010. [9] Samaneh Babayan-Mashhadi, and Reza Lotfi, “Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator,” IEEE Trans. VLSI Syst.,vol. 22, no. 2, Feb. 2014. [10] P. Nuzzo et al., “Noise analysis of regenerative comparators for reconfigurable ADC architectures,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 7, pp. 1441–1454, Jul. 2008. [11] Yao-Sheng Hu, Chi-Huai Shih, Hung-Yen Tai, Hung-Wei Chen and Hsin-Shu Chen, “A 0.6V 6.4fJ/conversion-step 10-bit 150MS/s Subranging SAR ADC in 40nm CMOS,” IEEE Asian Solid-State Circuits Conf. Dig. Tech. Papers, Kaohsiung, Taiwan, Nov. 2014. [12] C. C. Liu, S. J. Chang, G. Y. Huang, and Y. Z. Lin, “A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure,” IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 731–740, Apr. 2010. [13] J. H. Tsai, Y. J. Chen, M. H. Shen, and P. C. Huang, “A 1-V, 8b, 40MS/s, 113μW charge-recycling SAR ADC with a 14μW asynchronous controller,” Symp. VLSI Circuits Dig. Tech. Papers, pp. 264–265, Jun. 2011. [14] G.-Y. Huang, S.-J. Chang, C.-C. Liu, and Y.-Z. Lin, “10-bit 30-MS/s SAR ADC using a switchback switching method,” IEEE Trans. VLSI Syst., vol. 21, no. 3, pp. 584–588, Mar. 2013. [15] W.-H. Tsai et al., “A 10-bit-50MS/s SAR ADC for dual-voltage domain portable systems,” Proc. IEEE ISCAS, pp. 2425–2428, May. 2015. [16] Wen-Chia Luo, Soon-Jyh Chang, Chun-Po Huang, and Hao-Sheng Wu,” A 11-Bit 35-MS/s Wide Input Range SAR ADC in 180-nm CMOS Process,” Symp. VLSI-DAT, pp. 1-4, Apr. 2018. [17] Dejan Markovic´, Vladimir Stojanovic´, Borivoje Nikolic´, Mark A. Horowitz, and Robert W. Brodersen, “Methods for True Energy-Performance Optimization,” IEEE J. Solid-State Circuits, vol. 34, no. 5, Aug. 2004. [18] Mehdi Saberi, Reza Lotfi, Khalil Mafinezhad, and Wouter A. Serdijn ,“Analysis of Power Consumption and Linearity in Capacitive Digital-to-Analog Converters Used in Successive Approximation ADCs,” IEEE Trans. Circuits Syst., vol. 58, no. 8, Aug. 2011. [19] Chun-Po Huang, Jai-Ming Lin, Ya-Ting Shyu, and Soon-Jyh Chang,“A Systematic Design Methodology of Asynchronous SAR ADCs,” IEEE Trans. VLSI Syst., vol. 24, no. 5, May. 2016. [20] Ginsburg, B. P. and A. P. Chandrakasan, 'The Mixed Signal Optimum Energy Point: Voltage and Parallelism,' ACM/IEEE Design Automation Conference, pp. 244-249, Anaheim, CA, Jun. 2008. [21] Allen Waters1, Jason Muhlestein and Un-Ku Moon,“Analysis of Metastability Errors in Asynchronous SAR ADCs,” IEEE Electronics Conf., Circuits, and Systems ,Dec. 2015. [22] Zhu Z, Qiu Z and Liu M, “ A 6-to-10 bit 0.5 V-to-0.9 V reconfigurable 2 MS/s power scalable SAR ADC in 0.18 um CMOS,” IEEE Trans. Circuits Syst., Mar. 2015. [23] Prajit Nandi, Hirak Talukdar, Dhiraj Kumar and Ashvin Kumar G. Katakwar,” A Novel Approach to Design SAR-ADC: Design Partitioning Method,” IEEE Trans. Computer-Aided Design of Integrated Circuits Syst., Mar. 2016. [24] Yulin Zhang, Edoardo Bonizzoni and Franco Maloberti ,“Mismatch and Parasitics Limits in Capacitors-Based SAR ADCs,” IEEE Electronics Conf., Circuits and Systems (ICECS), Dec. 2016. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/70491 | - |
| dc.description.abstract | 連續漸進式暫存類比數位轉換器(SAR ADC)因為其良好的功耗效率而被廣泛應用於可攜式生醫電路系統。然而，SAR ADC的設計最佳化對許多電路工程師而言往往是非常耗費時間的。本論文提出一種基於電路行為模型的低功耗多通道交錯時序SAR ADC的系統化電路設計方法，目標是能夠輔助工程師評估一套SAR ADC電路規格的可行性。電路行為模型基於程式語言MATLAB，由不匹配模型、延遲模型、雜訊模型組成，行為模型透過Cadence Spectre的電晶體層級模擬來驗證，本文也提供基於一百八十奈米CMOS製程的設計範例以展示此設計方法的準確性。 | zh_TW |
| dc.description.abstract | Successive approximation register analog-to-digital converters (SAR ADCs) are widely used in portable biomedical electronic systems due to their excellent power efficiency. However, the design optimization of SAR ADCs is often very time-consuming for many circuit engineers. This paper proposes a systematic design methodology for low-power time-interleaved SAR ADCs based on circuit behavioral model, aiming to assist engineers to evaluate the feasibility of a given specification of SAR ADC. The circuit behavioral model is based on MATLAB and consisted of mismatch model, delay model and noise model. The behavioral model is verified through transistor-level simulation with Cadence Spectre. Design examples based on 0.18um CMOS technology are also provided to demonstrate the accuracy of this design methodology. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-17T04:29:22Z (GMT). No. of bitstreams: 1 ntu-107-R02943004-1.pdf: 3147694 bytes, checksum: 88290c1c66f997d873c921e8b440936c (MD5) Previous issue date: 2018 | en |
| dc.description.tableofcontents | 誌謝 i
摘要 ii ABSTRACT iii CONTENTS iv LIST OF FIGURES vii LIST OF TABLES x Chapter 1 前言 1 1.1 研究動機 1 1.2 論文架構 3 Chapter 2 SAR ADC的背景知識 5 2.1 前言 5 2.2 ADC效能指標 5 2.2.1 差分和積分非線性 (DNL，INL) 5 2.2.2 訊號雜訊比 (SNR) 8 2.2.3 訊號與雜訊失真比 (SNDR) 9 2.2.4 有效位元數 (ENOB) 10 2.2.5 無雜散動態範圍 (SFDR) 10 2.2.6 總諧波失真(Total Harmonic Distortion) 11 2.2.7 品質因數 (FoM) 11 2.3 各種類比數位轉換器架構介紹 11 2.3.1 子範圍 ADC(Subrange ADC) 11 2.3.2 連續漸進式暫存類比數位轉換器(SAR ADC) 12 2.3.3 交錯時序ADC(Time-interleaved ADC) 14 2. 4 交錯時序ADC的誤差來源………………………………………………15 2.4.1 Offset 不匹配 15 2.4.2 增益不匹配 16 2.4.3 時間偏斜 17 Chapter 3 電路行為模型(Behavioral Model) 19 3.1 前言 19 3.2 設計流程與行為模型的架構 19 3.2.1 設計流程 19 3.2.2 行為模型的實現 21 3.3 不匹配(Mismatch)模型 23 3.4 延遲模型 26 3.5 雜訊模型 30 3.6 速度-功耗抵換(Tradeoff)分析 33 3.7 多通道非線性度不匹配分析 34 Chapter 4 SAR ADC電路實作 37 4.1 前言 37 4.2 Coarse ADC和fine ADC 37 4.3 Bootstrapped開關 39 4.4 比較器 41 4.5 電容DAC 42 4.6 時脈產生器 47 4.7 數據暫存器與電容控制邏輯 48 4.8 比較器控制邏輯 50 Chapter 5 電路實作範例與結論 52 5.1 前言 52 5.2 十位元ADC電路實作結果 52 5.3 其他電路實作範例 55 5.3.1 100MHz、八位元SARADC 55 5.3.2 100MHz、九位元SARADC 57 5.4 結論 60 5.5 未來展望 60 REFERENCE 61 | |
| dc.language.iso | zh-TW | |
| dc.subject | 連續漸進式暫存 | zh_TW |
| dc.subject | 低功耗 | zh_TW |
| dc.subject | 行為模型 | zh_TW |
| dc.subject | behavioral model | en |
| dc.subject | low power | en |
| dc.subject | Successive-approximation register | en |
| dc.title | 一種低功耗多通道連續漸進式類比數位轉換器的設計方法 | zh_TW |
| dc.title | A Systematic Design Methodology of Low-Power Time-Interleaved SAR ADC | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 106-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 林宗賢(Tsung-Hsien Lin),黃柏鈞(Po-Chiun Huang) | |
| dc.subject.keyword | 連續漸進式暫存,低功耗,行為模型, | zh_TW |
| dc.subject.keyword | Successive-approximation register,low power,behavioral model, | en |
| dc.relation.page | 63 | |
| dc.identifier.doi | 10.6342/NTU201803064 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2018-08-13 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| Appears in Collections: | 電子工程學研究所 | |
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| File | Size | Format | |
|---|---|---|---|
| ntu-107-1.pdf Restricted Access | 3.07 MB | Adobe PDF |
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