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Title: | 位元滑動之AES門檻實作 Threshold Implementations of Bit-Sliding AES |
Authors: | Hung-Hsien Lee 李紘賢 |
Advisor: | 鄭振牟 |
Keyword: | AES,位元滑動,門檻實作,一階差分能量分析, AES, bit-sliding, threshold implementation, first-order differential power analysis, |
Publication Year : | 2018 |
Degree: | 碩士 |
Abstract: | 在有限資源的嵌入式裝置中,面積可能是實作的第一個考量。位元滑動的技術有效降低實作所使用的面積量。然而這些裝置易受功耗分析攻擊,在硬體上的傳統遮罩防護均勻地遮蔽了中間值,但在運算中間值的過程洩漏了資訊,電路上的毛刺成為了傳統遮罩防護的弊病。門檻實作在硬體上擁有更嚴格的條件。即使存在電路上的毛刺,門檻實作提供對抗一階攻擊的可證明安全性。我們在現場可程式邏輯閘陣列中實作位元滑動AES,並攻擊之。我們完成了抵擋一階攻擊的位元滑動AES之門檻實作,並與前人的AES門檻實作比較電路合成結果。 For those resource-limited embedded cryptographic devices, the area may be the first issue to the implementation. Bit-sliding or bit-serialized technique extremely makes the implementation area decrease. But these devices suffer from power analysis dramatically. In hardware, the traditional masking approach does mask the intermediate value uniformly but not in process of them. Glitches become a critical issue on those masking approach. As having stricter assumption in hardware, threshold implementations provide provable security against first-order attack even in the present of glitches. We attack the bit-sliding AES in the FPGA and complete its countermeasure against first-order attack. We also provide ASIC synthesis results of the threshold implementation of bit-sliding AES and compare it to related threshold implementations of AES. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/69132 |
DOI: | 10.6342/NTU201801794 |
Fulltext Rights: | 有償授權 |
Appears in Collections: | 電子工程學研究所 |
Files in This Item:
File | Size | Format | |
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ntu-107-1.pdf Restricted Access | 3.57 MB | Adobe PDF |
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