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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李建模 | |
| dc.contributor.author | Chih-Ming Chang | en |
| dc.contributor.author | 張志銘 | zh_TW |
| dc.date.accessioned | 2021-06-17T01:34:27Z | - |
| dc.date.available | 2020-08-11 | |
| dc.date.copyright | 2017-08-11 | |
| dc.date.issued | 2017 | |
| dc.date.submitted | 2017-08-01 | |
| dc.identifier.citation | [Abdollahi 07] Abdollahi, Afshin. 'Probabilistic decision diagrams for exact probabilistic analysis.' IEEE/ACM international conference on Computer-aided design, 2007.
[Cheemalavagu 05] S. Cheemalavagu, P. Korkmaz, K. V. Palem, B. E. S. Akgul, and L. N. Chakrapani, “A probabilistic CMOS switch and its realization by exploiting noise,” In Proc. Int. Conf. Very Large Scale Integr. Syst. Chip (VLSI-SoC), 2005. [CPLEX 14] IBM ILOG CPLEX Optimization Studio Community Edition, https://www-01.ibm.com/software/commerce/optimization/cplex-optimizer/ [Du 15] Du, Zidong, et al. 'Leveraging the error resilience of neural networks for designing highly energy efficient accelerators.' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015. [Hogg 97] Hogg, R.V. and Tanis, E.A. Probability and Statistical Inference, fifth Edition, Prentice-Hall, 1997. [Heydari 00] P. Heydari and M. Pedram. Analysis of jitter due to power-supply noise in phase-locked loops. In Proc. of the IEEE Custom Integrated Circuits Conference, 2000. [Han 05] Han, Jie, et al. 'Faults, error bounds and reliability of nanoelectronic circuits.' IEEE International Conference on. IEEE, 2005. [Huang 15] Huang, Ching-Yi, et al. 'Correctness Analysis and Power Optimization for Probabilistic Boolean Circuits.' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015. [ITRS 07] International Technology Roadmap for Semiconductors, “International technology roadmap for semiconductors 2007 edition”. [Kim 03] N. Kim, T. Austin, D. Blaauw, T. Mudge, K. Flautner, J. Hu, M. Irwin, M. Kandemir, and V. Narayanan. “Leakage current: Moore’s law meets static power.” IEEE Computer, 2003. [Krishnaswamy 07] Krishnaswamy, Smita, Igor L. Markov, and John P. Hayes. 'Tracking uncertainty with probabilistic logic circuit testing.' IEEE Design & Test of Computers, 2007. [Kim 14] Kim, Jaeyoon, and Sandip Tiwari. 'Inexact computing using probabilistic circuits: Ultra low-power digital processing.' ACM Journal on Emerging Technologies in Computing Systems (JETC), 2014. [Kim 16] Kim, Kyounghoon, et al. 'Dynamic energy-accuracy trade-off using stochastic computing in deep neural networks.' In Proc. of Annual Design Automation Conference, 2016. [McCluskey 00] McCluskey, Edward J., and Chao-Wen Tseng. 'Stuck-fault tests vs. actual defects.' Test Conference, 2000. [Mendoza 04] F. Mendoza-Hernandez, M. Linares-Aranda, and V. H. Champac-Vilela. “The noise immunity of dynamic digital circuits with technology scaling.” In Proc. of International Symposium on Circuits and Systems (ISCAS), 2004. [NanGate 09] NanGate Open Cell Library. Retrieved from http://www.nangate.com/, 2008. [Patel 03] Patel, Ketan N., Igor L. Markov, and John P. Hayes. 'Evaluating circuit reliability under probabilistic gate-level fault models.' In Proc. of the International Workshop on Logic and Synthesis, 2003. [Palem 03] K. V. Palem. “Energy aware algorithm design via probabilistic computing: from algorithms and models to Moores law and novel (semiconductor) devices.” In Proc. Intl. Conf. on Compilers, Architecture and Synthesis for Embedded Systems, 2003. [Palem 03] K. V. Palem. “Proof as experiment: Probabilistic algorithms from a thermodynamic perspective.” In Proc. Intl. Symposium on Verification (Theory and Practice), 2003. [Palem 03] K. V. Palem. Proceedings of International Symposium on Verification, 2003. [Palem 12] K. Palem and A. Lingamneni, “What to do about the end of Moore’s law, probably!” In Proc. Annu. Design Autom. Conf., 2012. [RICE 09] http://www3.ntu.edu.sg/home/zhkong/e3%20world%204_26Feb09_final.pdf [Rejimon 09] Rejimon, Thara, Karthikeyan Lingasubramanian, and Sanjukta Bhanja. 'Probabilistic error modeling for nano-domain logic circuits.' IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2009. [Sano 00] N. Sano. 'Increasing importance of electronic thermal noise in sub-0.1mm Si-MOSFETs.' The IEICE Transactions on Electronics, 2000. [Zscore 79] https://en.wikipedia.org/wiki/Standard_score | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/67489 | - |
| dc.description.abstract | Probabilistic circuits are very attractive for the next generation ultra-low power designs. It is important to test probabilistic circuits because a defect in probabilistic circuit may increase the erroneous probability. However, there is no suitable fault model and test generation/compression technique for probabilistic circuits yet. In this paper, a probabilistic fault model is proposed for probabilistic circuits. The number of faults is linear to the gate count. A statistical method is proposed to calculate the repetition needed for each test pattern. An integer linear programming (ILP) method is presented to minimize total test length, while keeping the same fault coverage. Experiments on ISCAS’89 benchmark circuits show the total test length of our proposed ILP method is 2.77 times shorter than a greedy method. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-17T01:34:27Z (GMT). No. of bitstreams: 1 ntu-106-R04943146-1.pdf: 1550079 bytes, checksum: 1a973867739ad5f91e4fb4a27e1b0217 (MD5) Previous issue date: 2017 | en |
| dc.description.tableofcontents | 摘要 i
Abstract ii Table of Contents iii List of Figures v List of Tables vi Chapter 3 Introduction 1 1.1 Motivation 1 1.2 Proposed Technique 7 1.3 Contribution 9 1.4 Organization 9 Chapter 4 Background 10 2.1 Erroneous Probability Evaluation 10 2.1.1 Probabilistic Transfer Matrix (PTM) 10 2.1.2 Probabilistic Gate Model 14 2.2 Hypothesis Testing 15 2.2.1 Binomial Distribution 16 2.2.2 Z-score 17 2.2.3 Hypothesis Testing 18 2.3 Previous Work about Probabilistic Circuits 21 Chapter 5 Proposed Techniques 25 3.1 Overall Flow 25 3.2 Probabilistic Fault Model 26 3.3 Probabilistic Fault Simulation 28 3.4 Probabilistic Fault Dictionary 29 3.4.1 Test Pattern Repetition Translation 30 3.4.2 Multiple-output Circuits 32 3.5 Linear Programming Model 34 3.5.1 Problem Definition 34 3.5.2 Objective Function and Constraints 35 3.5.3 Constraints and Terms Analysis 37 Chapter 6 Experimental Results 39 4.1 Experiment Setting and Benchmark Circuits 39 4.2 Comparison with Greedy Algorithm 41 4.3 Discussion 42 Chapter 7 Conclusion and Future Work 44 5.1 Conclusion 44 5.2 Future Work 44 References 46 | |
| dc.language.iso | en | |
| dc.subject | 機率電路 | zh_TW |
| dc.subject | 測試樣型壓縮 | zh_TW |
| dc.subject | 錯誤模型 | zh_TW |
| dc.subject | Probabilistic Circuit | en |
| dc.subject | Test Pattern Compression | en |
| dc.subject | Fault Model | en |
| dc.title | 機率電路測試圖樣壓縮 | zh_TW |
| dc.title | Test Pattern Compression for Probabilistic Circuit | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 105-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 黃俊郎(Jiun-Lang Huang),江介宏(Jie-Hung Jiang) | |
| dc.subject.keyword | 機率電路,測試樣型壓縮,錯誤模型, | zh_TW |
| dc.subject.keyword | Probabilistic Circuit,Test Pattern Compression,Fault Model, | en |
| dc.relation.page | 48 | |
| dc.identifier.doi | 10.6342/NTU201702295 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2017-08-02 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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