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標題: | 垂直式柱狀電晶體及鍺環繞式閘極電晶體之模擬研究 Simulation Study of Vertical Pillar Transistor and Ge Gate-All- Around FET |
作者: | Yu-Chun Yin 尹昱鈞 |
指導教授: | 劉致為 |
關鍵字: | 浮體效應,垂直式柱狀電晶體,無接面電晶體,鍺環繞式閘極電晶體, floating body effect,vertical pillar transistor,junctionless transistor,Ge Gate-All- Around FET, |
出版年 : | 2012 |
學位: | 碩士 |
摘要: | 對於未來最新一代的高密度4F2 陣列DRAM而言,垂直結構的單元電晶體(cell transistor)是必須的。垂直式柱狀電晶體因為具有非常好的閘極(gate)控制力而被認為是4F2 陣列單元電晶體的最佳選擇。但垂直式柱狀電晶體在操作時會有浮體效應(Floating Body Effect),這個效應會造成動態存取時間的損害。我們討論了浮體效應的物理機制且提出了解決的方法:1. 降低GIDL的漏電流 2. 利用SiGe層降低電洞的能障高度。在極小的元件尺寸下,無接面的電晶體可以在半導體厚度小於20 奈米的條件下被應用。因為他需要在電晶體通道被關閉時達成完全空乏(Fully depletion)的條件。我們提出了一種低漏電的無接面電晶體結構-部分隱埋式汲極設計 (Reccessed Drain Design)。GIDL被有效的降低且因為寄生的BJT電流被有效的控制所以電晶體具有良好的動態存取特性。
第二部分的研究主要是模擬一種最新製程的先進元件-鍺環繞式閘極電晶體。他具有三角形的通道。通道的寬度為52nm,有效閘極長度為183奈米且Ion/Ioff = 105, SS= 130mV/dec, and Ion=235 uA/um at -1V。根據TCAD的模擬和解析解的模型,三角形通道元件相較傳統的矩形通道元件於有更好的電性控制。在有更好的尺寸的微縮,包括元件的尺寸以及等效閘極氧化層厚度(Equivalent Oxide Thickness,EOT)和降低介面狀態密度(Interface State Density,Dit. )元件效能可以在為來有效的提升。 For next generation highly-integrated DRAMs, 4F2 cell array structure composed of a capacitor stacked vertically on a cell transistor is required. Vertical pillar transistor (VPT) is regarded as the most promising candidate for cell transistor in the 4F2 cell array architecture due to its excellent gate controllability which enhances the subthreshold characteristics. This cell transistor also shows excellent static retention characteristic, but the dynamic retention characteristic still need much improvement due to the floating body effect in cell transistor. We discuss the physical mechanism of floating body effect in the vertical pillar transistor and propose solutions: 1. to minimize GIDL current 2. to lower the height of the hole barrier between the body and the bit line by using SiGe layer at bottom source/drain. With aggressive device scaling, junctionless transistor can be applied when the body of semiconductor is thinner than 20 nm allowing for full depletion condition in the channel region as the device is turned off. We investigate the GIDL phenomena by simulation and demonstrate an extremely low leakage junctionless VPT with partially recessed drain design. The GIDL is well suppressed and the dynamic retention characteristic is also improved due to the suppressing BJT parasitic current during the variation of bit line bias. In the second part of the research, we simulate a new kind of advanced device, Ge gate-all-around FET. The fabricated triangular p-channel Ge FET with fin width (Wfin) of 52nm and Lg of 183nm has Ion/Ioff = 105, SS= 130mV/dec, and Ion=235 uA/um at -1V. Based on TCAD simulations and modeled by analytical solution, the triangular channel has better electrostatic control than the conventional rectangular FinFET. By proper scaling of the fin size, EOT, and Dit, further enhancements can be expected. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/64677 |
全文授權: | 有償授權 |
顯示於系所單位: | 電子工程學研究所 |
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