請用此 Handle URI 來引用此文件:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/64677
完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 劉致為 | |
dc.contributor.author | Yu-Chun Yin | en |
dc.contributor.author | 尹昱鈞 | zh_TW |
dc.date.accessioned | 2021-06-16T22:57:16Z | - |
dc.date.available | 2017-08-22 | |
dc.date.copyright | 2012-08-22 | |
dc.date.issued | 2012 | |
dc.date.submitted | 2012-08-09 | |
dc.identifier.citation | 1. Moore, G.E., Cramming more components onto integrated circuits (Reprinted from Electronics, pg 114-117, April 19, 1965). Proceedings of the Ieee, 1998. 86(1): p. 82-85.
2. C. Auth, C.A., A. Blattner, D. Bergstrom, M. Brazier, M. Bost, M. Buehler, V. Chikarmane, T. Ghani, T. Glassman, R. Grover, W. Han, , et al. A 22nm High Performance and Low-Power CMOS Technology Featuring Fully-Depleted Tri-Gate Transistors, Self-Aligned Contacts and High Density MIM Capacitors in VLSI. 2012. 3. Colinge, J.P., Multi-gate SOI MOSFETs. Microelectronic Engineering, 2007. 84(9-10): p. 2071-2076. 4. Lin, C.-H., Compact Modeling of Nanoscale CMOS, in Electrical Engineering and Computer Sciences2007, University of California at Berkeley. 5. Masetti, G., M. Severi, and S. Solmi, Modeling of Carrier Mobility against Carrier Concentration in Arsenic-Doped, Phosphorus-Doped, and Boron-Doped Silicon. Ieee Transactions on Electron Devices, 1983. 30(7): p. 764-769. 6. Lombardi, C., et al., A Physically Based Mobility Model for Numerical-Simulation of Nonplanar Devices. Ieee Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988. 7(11): p. 1164-1171. 7. Ancona, M.G. and G.J. Iafrate, Quantum Correction to the Equation of State of an Electron-Gas in a Semiconductor. Physical Review B, 1989. 39(13): p. 9536-9540. 8. Hurkx, G.A.M., D.B.M. Klaassen, and M.P.G. Knuvers, A New Recombination Model for Device Simulation Including Tunneling. Ieee Transactions on Electron Devices, 1992. 39(2): p. 331-338. 9. Kinam, K. and J. Gitae. Memory Technologies for sub-40nm Node. in Electron Devices Meeting, 2007. IEDM 2007. IEEE International. 2007. 10. Yongjik, P. and K. Kinam. COB stack DRAM cell technology beyond 100 nm technology node. in Electron Devices Meeting, 2001. IEDM Technical Digest. International. 2001. 11. Kim, D.H., et al. A mechanically enhanced storage node for virtually unlimited height (MESH) capacitor aiming at sub 70nm DRAMs. in Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International. 2004. 12. Song, K.W., et al., A 31 ns Random Cycle VCAT-Based 4F(2) DRAM With Manufacturability and Enhanced Cell Efficiency. Ieee Journal of Solid-State Circuits, 2010. 45(4): p. 880-888. 13. Maeda, S., et al. A Vertical Φ-shape Transistor (VΦT) cell for 1 Gbit DRAM and beyond. in VLSI Technology, 1994. Digest of Technical Papers. 1994 Symposium on. 1994. 14. Hofmann, F. Surrounding gate select transistor for 4F stacked Gbit DRAM. in ESSDERC 2001. 15. Yoon, J.-M. A novel low leakage current VPT(vertical pillar transistor) integration for 4F2 DRAM cell array with sub 40 nm technology. in DRC Tech. Dig. 2006. 16. Hyunwoo, C., et al. Novel 4F2 DRAM cell with Vertical Pillar Transistor(VPT). in Solid-State Device Research Conference (ESSDERC), 2011 Proceedings of the European. 2011. 17. Jae-Man, Y., et al. A Novel Low Leakage Current VPT(Vertical Pillar Transistor) Integration for 4F2 DRAM Cell Array with sub 40 nm Technology. in Device Research Conference, 2006 64th. 2006. 18. Yeo, Y.-C. and J. Sun, Finite-element study of strain distribution in transistor with silicon–germanium source and drain regions. Applied Physics Letters, 2005. 86(2): p. 023103-023103-3. 19. Sungjoo, H. Memory technology trend and future challenges. in Electron Devices Meeting (IEDM), 2010 IEEE International. 2010. 20. Yoshimi, M., et al., Suppression of the floating-body effect in SOI MOSFET's by the bandgap engineering method using a Si1-xGex source structure. Ieee Transactions on Electron Devices, 1997. 44(3): p. 423-430. 21. Nishiyama, A., O. Arisumi, and M. Yoshimi, Suppression of the floating-body effect in partially-depleted SOI MOSFET's with SiGe source structure and its mechanism. Ieee Transactions on Electron Devices, 1997. 44(12): p. 2187-2192. 22. Date, C.K. and J.D. Plummer, Suppression of the floating-body effect using SiGe layers in vertical surrounding-gate MOSFETs. Ieee Transactions on Electron Devices, 2001. 48(12): p. 2684-2689. 23. Date, C.K. and J.D. Plummer. SiGe heterojunctions in epitaxial vertical surrounding-gate MOSFETs. in VLSI Technology, 2000. Digest of Technical Papers. 2000 Symposium on. 2000. 24. Kah Wee, A., et al. Enhanced performance in 50 nm N-MOSFETs with silicon-carbon source/drain regions. in Electron Devices Meeting, 2004. IEDM Technical Digest. IEEE International. 2004. 25. Colinge, J.P., et al., Nanowire transistors without junctions. Nature Nanotechnology, 2010. 5(3): p. 225-229. 26. Lee, C.W., et al., Junctionless multigate field-effect transistor. Applied Physics Letters, 2009. 94(5). 27. Lee, C.W., et al., Performance estimation of junctionless multigate transistors. Solid-State Electronics, 2010. 54(2): p. 97-103. 28. Colinge, J.P., et al., Junctionless Nanowire Transistor (JNT): Properties and design guidelines. Solid-State Electronics, 2011. 65-66: p. 33-37. 29. Colinge, J.P., et al., Junctionless Transistors: Physics and Properties Semiconductor-On-Insulator Materials for Nanoelectronics Applications, A. Nazarov, et al., Editors. 2011, Springer Berlin Heidelberg. p. 187-200. 30. Kranti, A., et al. Junctionless nanowire transistor (JNT): Properties and design guidelines. in Solid-State Device Research Conference (ESSDERC), 2010 Proceedings of the European. 2010. 31. Takagi, S., et al., On the Universality of Inversion Layer Mobility in Si Mosfets .1. Effects of Substrate Impurity Concentration. Ieee Transactions on Electron Devices, 1994. 41(12): p. 2357-2362. 32. Takagi, S., et al., On the Universality of Inversion Layer Mobility in Si Mosfets .2. Effects of Surface Orientation. Ieee Transactions on Electron Devices, 1994. 41(12): p. 2363-2368. 33. Thompson, S.E., et al., A 90-nm logic technology featuring strained-silicon. Ieee Transactions on Electron Devices, 2004. 51(11): p. 1790-1797. 34. Jacoboni, C., et al., A review of some charge transport properties of silicon. Solid-State Electronics, 1977. 20(2): p. 77-89. 35. Yan, R.H., A. Ourmazd, and K.F. Lee, Scaling the Si Mosfet - from Bulk to Soi to Bulk. Ieee Transactions on Electron Devices, 1992. 39(7): p. 1704-1710. 36. Suzuki, K., et al., Scaling Theory for Double-Gate Soi Mosfets. Ieee Transactions on Electron Devices, 1993. 40(12): p. 2326-2329. 37. Frank, D.J., Y. Taur, and H.S.P. Wong, Generalized scale length for two-dimensional effects in MOSFET's. Ieee Electron Device Letters, 1998. 19(10): p. 385-387. 38. Liang, X.P. and Y. Taur, A 2-d analytical solution for SCEs in DG MOSFETs. Ieee Transactions on Electron Devices, 2004. 51(9): p. 1385-1391. 39. Tsormpatzoglou, A., et al., Semi-analytical Modeling of short-channel effects in Si and Ge symmetrical double-gate MOSFETs. Ieee Transactions on Electron Devices, 2007. 54(8): p. 1943-1952. 40. Taur, Y. and T.H. Ning, Fundamentals of Modern VLSI Devices 2nd edition2009. 41. Takagi, S., et al. Channel structure design, fabrication and carrier transport properties of strained-Si/SiGe-on-insulator (strained-SOI) MOSFETs. in Electron Devices Meeting, 2003. IEDM '03 Technical Digest. IEEE International. 2003. 42. Lee, J.W., et al., Mobility analysis of surface roughness scattering in FinFET devices. Solid-State Electronics, 2011. 62(1): p. 195-201. 43. Pei, G., et al., FinFET design considerations based on 3-D simulation and analytical modeling. Ieee Transactions on Electron Devices, 2002. 49(8): p. 1411-1419. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/64677 | - |
dc.description.abstract | 對於未來最新一代的高密度4F2 陣列DRAM而言,垂直結構的單元電晶體(cell transistor)是必須的。垂直式柱狀電晶體因為具有非常好的閘極(gate)控制力而被認為是4F2 陣列單元電晶體的最佳選擇。但垂直式柱狀電晶體在操作時會有浮體效應(Floating Body Effect),這個效應會造成動態存取時間的損害。我們討論了浮體效應的物理機制且提出了解決的方法:1. 降低GIDL的漏電流 2. 利用SiGe層降低電洞的能障高度。在極小的元件尺寸下,無接面的電晶體可以在半導體厚度小於20 奈米的條件下被應用。因為他需要在電晶體通道被關閉時達成完全空乏(Fully depletion)的條件。我們提出了一種低漏電的無接面電晶體結構-部分隱埋式汲極設計 (Reccessed Drain Design)。GIDL被有效的降低且因為寄生的BJT電流被有效的控制所以電晶體具有良好的動態存取特性。
第二部分的研究主要是模擬一種最新製程的先進元件-鍺環繞式閘極電晶體。他具有三角形的通道。通道的寬度為52nm,有效閘極長度為183奈米且Ion/Ioff = 105, SS= 130mV/dec, and Ion=235 uA/um at -1V。根據TCAD的模擬和解析解的模型,三角形通道元件相較傳統的矩形通道元件於有更好的電性控制。在有更好的尺寸的微縮,包括元件的尺寸以及等效閘極氧化層厚度(Equivalent Oxide Thickness,EOT)和降低介面狀態密度(Interface State Density,Dit. )元件效能可以在為來有效的提升。 | zh_TW |
dc.description.abstract | For next generation highly-integrated DRAMs, 4F2 cell array structure composed of a capacitor stacked vertically on a cell transistor is required. Vertical pillar transistor (VPT) is regarded as the most promising candidate for cell transistor in the 4F2 cell array architecture due to its excellent gate controllability which enhances the subthreshold characteristics. This cell transistor also shows excellent static retention characteristic, but the dynamic retention characteristic still need much improvement due to the floating body effect in cell transistor. We discuss the physical mechanism of floating body effect in the vertical pillar transistor and propose solutions: 1. to minimize GIDL current 2. to lower the height of the hole barrier between the body and the bit line by using SiGe layer at bottom source/drain. With aggressive device scaling, junctionless transistor can be applied when the body of semiconductor is thinner than 20 nm allowing for full depletion condition in the channel region as the device is turned off. We investigate the GIDL phenomena by simulation and demonstrate an extremely low leakage junctionless VPT with partially recessed drain design. The GIDL is well suppressed and the dynamic retention characteristic is also improved due to the suppressing BJT parasitic current during the variation of bit line bias.
In the second part of the research, we simulate a new kind of advanced device, Ge gate-all-around FET. The fabricated triangular p-channel Ge FET with fin width (Wfin) of 52nm and Lg of 183nm has Ion/Ioff = 105, SS= 130mV/dec, and Ion=235 uA/um at -1V. Based on TCAD simulations and modeled by analytical solution, the triangular channel has better electrostatic control than the conventional rectangular FinFET. By proper scaling of the fin size, EOT, and Dit, further enhancements can be expected. | en |
dc.description.provenance | Made available in DSpace on 2021-06-16T22:57:16Z (GMT). No. of bitstreams: 1 ntu-101-R99943063-1.pdf: 2424629 bytes, checksum: 0340d98d1c12fa3398a5a59d6ebc812e (MD5) Previous issue date: 2012 | en |
dc.description.tableofcontents | CONTENTS
口試委員會審定書 # 中文摘要 ii ABSTRACT iii CONTENTS iv LIST OF FIGURES vii Chapter 1 Introduction 1 1.1 Advantage of MOSFET Scaling Down 1 1.2 Advanced MOSFETs structures 3 Chapter 2 Physical Models 4 2.1 Introduction 4 2.2 Transport Equation 4 2.2.1 Governing equations for device physics 4 2.2.2 Drift-diffusion equation 5 2.3 Mobility Models 6 2.3.1 Mobility Models Combination 6 2.3.2 Mobility Due to Lattice Scattering (Constant mobility model) 7 2.3.3 Doping-Dependent Mobility Degradation (Masetti Model) 7 2.3.4 Mobility Degradation at Si-Insulator Interface 8 2.4 Quantization Model 9 2.5 Generation and Recombination 10 2.5.1 Shockley–Read–Hall recombination (SRH) 10 2.5.2 Band–To–Band Tunneling Model (BTBT) 11 Chapter 3 Vertical Pillar Transistors for High Density DRAM 13 3.1 Introduction 13 3.2 Device Structure 20 3.3 I-V Transfer Characteristics 20 3.4 SiliconGermanium Layer in Bottom Source/Drain (Floating Body Effect) 23 3.5 Mixed Mode Transient Simulation 26 3.6 Insert Channel Design 28 Chapter 4 Junctionless Vertical Pillar Transistors 30 4.1 Introduction 30 4.1.1 Device structure of the junctionless transistor 31 4.1.2 Conduction mechanism of the junctionless transistor 32 4.1.3 Mobility 36 4.2 Low Leakage Design: Recessed Drain 38 4.2.1 Introduction 38 4.2.2 Device Structure 39 4.2.3 Comparison between the junctionless device and the inversion-mode device 40 4.2.4 Effect of the diameter of the r-drain and the thickness of the replacement oxide thickness 42 4.2.5 Distribution of electric field and band-to-band tunneling generation rate 45 4.2.6 Mixed mode transient simulation 47 Chapter 5 Simulation Study of Ge on SOI Gate-all-around FET 48 5.1 Analysis of short channel effect of the double gate device by 2D analytical solution 48 5.1.1 The 2D analytical solution for short channel effect in double gate MOSFETs 48 5.2 Simulation study of Ge on SOI gate-all-around FET 51 5.2.1 Introduction 52 5.2.2 Experimental results 52 5.2.3 Device performance and simulation 54 Chapter 6 Summary and Future Work 62 6.1 Summary 62 6.2 Future work 63 Reference 64 | |
dc.language.iso | en | |
dc.title | 垂直式柱狀電晶體及鍺環繞式閘極電晶體之模擬研究 | zh_TW |
dc.title | Simulation Study of Vertical Pillar Transistor and Ge Gate-All- Around FET | en |
dc.type | Thesis | |
dc.date.schoolyear | 100-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 許舒涵,李敏鴻,林鴻志 | |
dc.subject.keyword | 浮體效應,垂直式柱狀電晶體,無接面電晶體,鍺環繞式閘極電晶體, | zh_TW |
dc.subject.keyword | floating body effect,vertical pillar transistor,junctionless transistor,Ge Gate-All- Around FET, | en |
dc.relation.page | 68 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2012-08-09 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
文件中的檔案:
檔案 | 大小 | 格式 | |
---|---|---|---|
ntu-101-1.pdf 目前未授權公開取用 | 2.37 MB | Adobe PDF |
系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。