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Title: | Optimal Ate pairing 的硬體實作 A hardware implementation of the optimal Ate pairing on a 256-bit Barreto-Naehrig curve |
Authors: | Yun-An Chang 張運安 |
Advisor: | 鄭振牟 |
Keyword: | Optimal Ate pairing,Barreto-Naehrig 曲線,特定應用積體電路實作, Optimal Ate pairing,Barreto-Naehrig Curve,ASIC implementation, |
Publication Year : | 2013 |
Degree: | 碩士 |
Abstract: | Bilinear pairings on elliptic curves have many applications in both constructive cryptography and cryptanalysis. Pairing computation is much more complicated compared to that of other popular public-key cryptosystems. Efficient implementation of cryptographic pairing has thus received increasing interest, both from software and hardware approaches, pursuing higher speed or, in the cases of hardware implementation, smaller time-area product. In
this paper, we will present the design and implementation of a programmable cryptographic coprocessor that supports various pairings at 128-bit security level. Unlike the general architecture, our design is optimized for carrying out pairing computation over fields of large characteristics. As a result, our design stays competitive even compared with specialized implementations in terms of time-area product. For example, we will show that by using heterogeneous arithmetic units, we can achieve a significant speed-up for pairing computation over Barreto-Naehrig curves, resulting in an implementation that achieves a latency of 3.58 ms with a gate count of around 156K. To the best of our knowledge, this is the smallest time-area product achieved among all implementations of optimal ate pairing using application-specific integrated circuits. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/62366 |
Fulltext Rights: | 有償授權 |
Appears in Collections: | 電機工程學系 |
Files in This Item:
File | Size | Format | |
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ntu-102-1.pdf Restricted Access | 2.09 MB | Adobe PDF |
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