針對次22奈米技術之微影最佳化

Abstract

隨著積體電路晶片技術進入次22奈米製程的時代，積體電路設計面臨嚴峻的物理極限挑戰。林本堅博士於2012年國際實體設計研討會上提到三項未來有可能突破微影極限之技術：多圖案微影、電子束微影以及極紫外光微影。然而，各技術皆面臨不同的實體設計困境，並急需解決之道 多圖案微影為最有希望突破傳統光學微影解析度極限的技術之一。除了常見的雙微影蝕刻雙圖案微影技術之外，自動對準雙圖案微影技術因其較佳之疊層對準及關鍵尺寸控制能力，於近年受到更多的關注。利用自動對準雙圖案微影技術，佈局分解步驟分為兩種形式：正型佈局分解及負型佈局分解。正型佈局分解利用間隙壁直接定義電路圖案並且搭配一個切除光罩做出最終電路佈局；而負型佈局分解中的間隙壁則定義電路圖案間的間隔，並搭配一個修剪光罩以完成電路。相較於負型佈局分解，正型佈局分解對於無網格設計有較好的佈局分解能力；然而，目前並無研究為正型佈局分解設計演算法。在此論文中，我們提出第一個為自動對準雙圖案微影技術設計的正型佈局分解演算法，此演算法可以同時將核心光罩及切除光罩上的圖案衝突數目最小化。 傳統光學微影之外，有兩種最有希望的下一世代微影技術：電子束微影以及極紫外光微影。電子束微影因其不受限於光的繞射效應，電子束可以定義非常微小且解析度高的電路圖案。然而，電子束微影有兩項重大的問題，一個是因高能量電子束所造成的熱效應，另一個是低生產量的問題。使用於光罩製造的單一電子束微影系統，通常以鄰近連續的方式做電子束直寫，此直寫方式易累積大量熱能於小部分區域，進而造成關鍵尺寸失真。針對這個問題，我們利用圖論演算法提出一子域排程演算法將子域直寫順序重新排序，並且同時考慮每個子域的封鎖區域以減緩熱問題。 單一電子束微影系統因其相當低的生產量並不適用於晶片之量產，近年來多電子束微影系統相繼被提出，其利用數千或更多的電子束以平行的方式同時直寫電路圖案以大大地增進生產量。由於多電子束微影系統平行直寫的方式，一個電路佈局會先被切割成長條區域，我們將長條區域的邊界定義為縫線。被縫線切割到的電路圖案會由不同的電子束直寫，因此會受到對準誤差的影響。為了減少縫線造成的電路圖案嚴重失真，我們於此論文中提出第一個考慮縫線的繞線演算法，進而產生利於多電子束微影的電路設計。 另一方面，極紫外光微影是另一個很有機會的下一世代微影技術，其利用比傳統光學微影波長短十倍的光源增進解析度。然而，由於極紫外光微影系統零件表面的粗糙不平，大量散射的光，也就是閃焰，成為最嚴重的問題之一。此外，因電路佈局密度不平均以及閃焰邊緣效應（閃焰於晶片邊緣的分布與晶片中心的分布相當地不同）也造成大量的閃焰差異量。大量的閃焰和閃焰差異量都會造成控制關鍵尺寸平均度的困難，因此，針對此問題，我們提出第一個考慮總體閃焰分布的虛擬填充演算法以減緩極紫外光的閃焰效應。

As integrated circuit (IC) process nodes continue to shrink to 22nm and below, the IC industry will face severe manufacturing challenges with conventional optical lithography technologies. According to the keynote speech at International Symposium on Physical Design (ISPD) 2012 by Dr. Burn J. Lin from TSMC, three possible technologies may push the limits of lithography: multiple patterning lithography, electron beam lithography (EBL) and extreme ultraviolet lithography (EUVL). However, each of which encounters different design difficulties and requires solutions for a breakthrough. For overcoming the resolution limit of conventional optical lithography, multiple patterning lithography has been regarded as one of the most promising solutions. While litho-etch-litho-etch (LELE) double patterning lithography (DPL) has been widely used, self-aligned double patterning (SADP) has received more and more attention in recent years due to its better controllability of overlay and critical dimension (CD) uniformity. Two types of layout decomposition strategies are used to define two-dimensional layout patterns in SADP: positive and negative tones, in which spacers respectively define layout patterns with a cut mask and define spacings among patterns with a trim mask. Several algorithms have been proposed for negative tone layout decomposition. To the best of our knowledge, however, no algorithm has been proposed for positive tone layout decomposition, which could have the better decomposability for gridless designs. In this dissertation, we propose the first work of positive tone layout decomposition for SADP which can simultaneously minimize the conflicts on both the core mask and the cut mask. In addition to the conventional optical lithography, there are two most promising Next Generation Lithography (NGL) technologies: EBL and EUVL. Since EBL is not limited by light diffraction, the e-beam can define very fine, high resolution patterns in a resist. There are two critical issues in EBL: (1) the thermal problem and (2) the low throughput. For a single e-beam system for photomask fabrication, the e-beam writing process is usually performed in a contiguously sequential way, causing the high-voltage beam to deposit a considerable amount of heat in a small area and resulting in critical dimension (CD) distortion. To avoid the successive heating problem in EBL, we propose a graph-based subfield scheduling algorithm that reorders the sequence of the writing process with blocked box consideration. The other critical issue in the single e-beam system is the extremely low throughput due to the maskless direct write process. Recently, the concept of multiple e-beam lithography (MEBL) has been proposed, which utilizes massively parallel exposures with thousands or even millions of beams to dramatically improve the throughput. Due to the deflection limitation of each beam and parallel writing strategies in MEBL, a layout (a main field) is split into stripes (subfields), and we define the stripe boundaries as the stitching lines. A pattern cut by a stitching line suffers from overlay error between two beams or two writing passes, and the overlay error causes different impacts on different types of patterns. To reduce stitching line-induced bad patterns, we propose the first work of stitch-aware routing algorithms for generating MEBL-friendly designs. On the other hand, EUVL is the other probable NGL technology since the ten times reduction in wavelength used in EUVL offers the capability of a continuation of Moore's law beyond the 22 nm technology node. However, due to the surface roughness of the optical system in EUVL, the rather high level of flare (i.e., scattered light) becomes one of the most critical issues. In addition, the layout density non-uniformity and the flare periphery effect (the flare distribution at the periphery is much different from that in the center of a chip) also induce a large flare variation within a layout. Both of the high flare level and the large flare variation could worsen the control of CD uniformity, and thus flare compensation strategies are required. In the dissertation, we also present the first work that solves the flare mitigation problem in EUVL with a specific dummiffication algorithm flow considering global flare distribution.