用於記錄系統之低密度奇偶檢查碼研究

Abstract

在高效率的調變與錯誤更正碼之中，任意翻轉法(deliberate flipping)根據 持續長度限制法則(Run-Length-Limited constraint)附加錯誤位元於寫入端資 料。在讀取端，高編碼率限制RLL錯誤位元的更正能力。在本篇論文中，我 們使用低密度奇偶檢查碼(LDPC)對於RLL限制儲存系統，主要進行兩種研究 主題包括RLL翻轉位元偵測和不均勻保護能力系統設計。首先，我們簡介傳 統任意翻轉法的寫入端與翻轉位元偵測的讀取端。接著，我們描述儲存系統 通道的特性與模型。這兩種研究主題，分別說明如下: 在第一項研究主題，RLL 翻轉位元偵測包含兩種方法改善系統的錯誤效 能。第一種方法是減少偵測錯誤所造成的影響透過調整軟式資訊量，這項方 法分別為抹除操作法，修剪操作法和平均修剪操作法。我們應用EXIT 特性 來顯示此方法的效能分析。第二種方法是增加正確偵測的可能性透過翻轉位 元演算法，其中演算中使用RLL 限制法則與LDPC 碼的冗餘檢查。因此，透 過傳統式的反轉位元LDPC 解碼法來提供可靠度測量改善偵測準確度。此改 善方法是為了RLL 偵測所設計。上述兩種方法可以合併起來改善錯誤更正效 能。 此外，傳統多階層編碼調變的不均勻保護系統已被研究來作為我們的參 考依據。訊息串列包含幾種不同的重要程度以及需要不同更正能力來保護對 抗雜訊。不均勻保護能力系統設計方針在設計時須了解以便於設計好的系統 效能。因此，再第二項研究主題，我們循著過去的設計思維使用不規則式的 LDPC 碼所具有的不均勻保護能力，來設計能更正RLL 錯誤的系統。我們藉 由一種分配技術去限制翻轉位元的出現位置且設定此位置具有較強壯的保護 能力。此外，我們設計訊號符號對應來減少相鄰鄰居的數目達到減少干擾以 增強強壯更正能力的位元。接著，我們推倒密度演進方程式來改善LDPC 碼 的效能。再者，EXIT 特性分析推薦的碼分佈具有的優點。最佳化過程透過差 分演化法來找到我們設計的系統的最佳碼分佈。

For efficient modulation and error control coding, the deliberate flipping approach impose the run-length-limited(RLL) constraint by bit error before recording. From the read side, high coding rate limits the correcting capability of RLL bit error. In this thesis, we study the low-density parity-check (LDPC) coding for RLL constrained recording system based on two main research topics including the RLL flipped bit detection and the unequal protection coding scheme design. For the fi rst topic, the detection of RLL flipped bit is provided by two approaches for enhancing the error performance of such a system. The first approach is to alleviate the negative effect of incorrect estimation of the flipped bits by adjusting the soft information. These methods are organized as erase operation, clipping operation and average clipping operation. We apply EXIT characteristic to illustrate the performance evaluation of the proposed method. The second approach is to increase the likelihood of the correct detection of flipped bits by designing a flipped-bit detection algorithm that utilizes both the RLL constraint and the parity-check constraint of the LDPC code. Hence, the detection accuracy is enhanced by providing the reliability measurement from conventional bit flipping decoding for LDPC code. The modi fied measurement is designed for RLL detection. These two approaches can be combined to obtain signifi cant improvement in BER performance over previously proposed methods. For the second topic, UEP capability of irregular-LDPC codes are used for recovering flipped bits. We provide an allocation technique to limit the occurrence of flipped bit on the bit with robust correction capability. In addition, we consider the signal labeling design to decrease the number of nearest neighbor for enhancing the robust bit. We also apply the density evolution technique to the the proposed system for evaluating the code performances. In addition, we utilize the EXIT characteristic to reveal the decoding behavior of the recommended code distribution. Finally, the optimization approach for the the best distribution is proven by differential evolution for the proposed system.