鍺/二氧化鍺介面及二氧化鍺塊材之第一原理探討以及矽鍺鰭式場效電晶體之電子遷移率計算

Abstract

由於互補式金氧半元件的尺寸不斷微縮，為了讓摩爾定律繼續延續下去，使用新穎材料已是無法避免的趨勢。在諸多已被提出的新材料中，鍺被認為極有可能取代矽成為下一世代p通道金氧半元件的製造材料。然而，要付諸大量生產，鍺仍有問題待解決，其中之一，便是鍺與介電材料的介面品質不佳。在許多解決方法之中，使用熱氧化法成長的二氧化鍺，由於可以有效降低鍺元件的介面缺陷密度，因此受到了許多關注。但鍺與二氧化鍺介面也還有未解的問題─過去的模擬結果顯示，在使用含有無缺陷鍺次級氧化物的氧化鍺與鍺所建立的介面模型中，並沒有發現任何介面帶隙能態，意味著單純的鍺次級氧化物並不是造成元件特性降低的來源。因此，在本論文中，我們決定採取第一原理密度泛函的方法來建立具有懸浮鍵的鍺/二氧化鍺介面模型，進一步探討介面上處在不同氧化態的鍺原子─也就是鍺次級氧化物中的鍺原子─之上的懸浮鍵所造成的帶隙能態能量位置的差異，還有不同氧化態對能量位置的影響，藉以提出能帶中不同位置之帶隙能態的可能來源，同時我們也解釋了在二氧化鍺中的氧化層固定電荷來源。此外，由於預期高介電常數金屬氧化物在未來極有可能被運用在鍺元件上，我們也研究了高介電材料內的金屬離子對鍺/二氧化鍺介面上帶隙能態可能產生的影響，並提出方法來幫助選擇適用於鍺元件的高介電氧化物。 本論文的第二部份，我們把焦點轉移到另一種可以幫助維持摩爾定律的技術─鰭式場效電晶體(FinFET)。我們模擬了在不同鍺/矽濃度比例下，矽鍺鰭式場效電晶體之電子遷移率變化。在我們的模擬中考慮了三種電子散射機制：聲子散射、粗糙表面散射以及矽鍺合金散射，矽鍺合金的散射位能井我們由似合實驗數據得到。此外，我們也討論了沿著鰭式通道的寬度和通道方向施加應力造成的電子遷移率上升變化。我們的計算結果對於如何選擇適當的應力施加方向來最佳化矽鍺鰭式場效電晶體的電子遷移率提供了策略。

Due to the aggressive scaling of CMOS technology, applying high mobility materials to channel of metal-oxide-semiconductor field-effect transistors (MOSFETs) is an important way to preserve the validity of Moore's Law. Among all the choices, Ge has been regarded as a promising candidate for p-channel device. However, an important issue concerning Ge MOSFETs is the electrical condition of the germanium/dielectric interface. As a result, germanium oxide (GeO2) is used as the potential passivation layer since the densities of interface states (Dit) can be reduced effectively by the methods of thermal oxidation. Nevertheless, one of the remaining puzzles is that the electronic structure of Ge/GeO2 interface models including a defect-free suboxide transition region did not reveal any gap states within the Ge band gap, suggesting that the suboxide itself should not be invoked as the cause of any electrical degradation. Therefore, in this work, by employing first-principle density functional theory (DFT) method, we investigate the electronic structure of Ge/GeO2 with Ge dangling bonds at different oxidation states to show the origin of the defect states at different energy locations and the shift of defect states within the bandgap due to higher oxidation state, and also explain the source of the positive fixed charges in defective GeO2 for the first time by calculating formation energy. Expecting the future high-k dielectric integration with Ge MOSFET, we also take a look at the impact of several kinds of high-k metal impurities on the gap states at Ge/GeO2 interface. This helps pave a way to find the optimal high-k oxides for Ge transistors. In the second phase of this work, we switch the focus to another approach which can also keep Moore's law going: FinFET. We simulate the electron mobility of SiGe FinFETs with different [Ge]/[Si] ratios, while taking into account three scattering mechanisms: phonon scattering, surface roughness scattering, and SiGe alloy scattering. We extract the alloy scattering potential from experimental data. In addition, the enhancement of mobility under stress along fin-width and channel direction as well as the fin-width effect on mobility are also investigated. Our results demonstrate a possible strategy to optimize the mobility of SiGe FinFETs via strain engineering at certain Ge concentration.