基於FSM錯誤模型所開發之RTL Design除錯技術

Abstract

給定一個錯誤的暫存器轉換階層設計以及一條顯示設計與規格不符的錯誤軌跡，自動除錯技術藉由此錯誤軌跡與暫存器轉換階層設計中模擬的結果，找出在暫存器轉換階層設計中可能的錯誤根源。值得注意的是，在現今極端複雜的超大積體電路設計中，幾乎不可能不利用自動化技術來進行除錯。如此，自動除錯技術在設計能否成功被完成中扮演著很重要的腳色。然而，這些自動除錯工具實際上並沒有如預期的受歡迎。最主要的原因是這些自動除錯工具產生極大量的可能錯誤根源，使得工程師必須花費大量的時間過濾這些可能錯誤根源。更糟糕的是，自動除錯工具所找到的可能錯誤根源大部分都是位於合成後的電路上，要從這些在合成後電路上的可能錯誤根源推論出暫存器轉換階層設計中的錯誤，對工程師而言相當費時。為了解決這個問題，我們提出一個自動暫存器轉換階層設計除錯演算法，這個演算法作用在基於有限狀態機的錯誤模型中。我們並沒有在合成後的電路上找尋可能錯誤根源，而是將可能發生在暫存器轉換階層設計上的錯誤，依照這些錯誤在其有限狀態機上的錯誤加以分類。這些可能錯誤根源能夠直接對應到原始的暫存器轉換階層程式碼中。實驗結果顯示，藉由我們的有限狀態基錯誤模型，我們的演算法能夠有效地在少數可能錯誤根源中偵測出真正的錯誤。

Given an erroneous RTL design and an error trace that demonstrates a mismatch between the specification and the design, automated design debugging techniques utilize this error trace and its simulation values on the circuit netlist to identify the potential error locations in the RTL design. Notably, with the extreme high complexity of modern VLSI designs, it is virtually impossible to debug the designs without the help of automated algorithms. Therefore, automated design debugging plays a very important role in ensuring the successful design sign-off. However, in reality these automated debugging tools are not as popular as they should be. The main reason is because they are notorious for generating results with a huge number of error candidates. Consequently, designers have to spend a very long time to screen out the spurious error candidates manually. What is worse, as the error candidates are mostly annotated on the circuit netlist, it is also very time-consuming for the designers to figure out the actual causes of the error on the original RTL design by tracing the error locations in the circuit implementation. To conquer these problems, we propose an automated RTL debugging algorithm that works on the FSM-based error models. Instead of representing the error candidates in a circuit implementation, we classify the potential errors of a RTL design by considering different error scenarios on its corresponding finite-state machine model. These error candidates can then be directly mapped to error locations in the original RTL code. The experimental results show that our algorithm is able to effectively identify the actual errors among a small number of error candidates with our finite-state machine error model.