利用集總節點分析電源完整性與去耦合電容最佳化擺置

Abstract

本論文提出集總節點分析法的方法，以分析設計一個系統的電源完整性。近年來，印刷電路板的設計變得越來越複雜，電源供應網路的輸入阻抗也變得越來越低。一般來說，去耦合電容可以被應用於降低電源供應網路的輸入阻抗然而在目前的工業電腦當中，有許多不需要的去耦合電容被使用，不僅僅會造成設計上的困難，而且也會也增加設計的成本，以及印刷電路板當中的使用的面積。 因此，本論文提出了一個新的集總節點分析法，進行去耦合電容的最佳化，並實際應用於目前的高速數位系統。不僅僅改善印刷電路板的輸入阻抗，也減少了去耦合電容的數量。 本文將詳細介紹其原理以及流程，並進行模擬以及實驗比較，證實本法的正確性。

This thesis presents a simple method to analyze and optimize the power integrity of high-speed digital systems. Modern PCB (print circuit board) design becomes more complex, since target impedance of the PDN (power distribution network) is getting lower in recent years. The decoupling capacitors can be used to maintain the impedance, but sometimes there are a lot of unnecessary decoupling capacitors, leading to increased design difficulty, cost, and PCB size. A simple optimization method based on a called lumped node analysis is proposed to deal with decoupling capacitors design. The analysis can reduce the number of decoupling capacitors with better input impedance. Both simulation and experimental results are presented to validate the method. Besides, the design flow and the theory are also discussed in detail.