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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/60495完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 吳瑞北(Ruey-Beei Wu) | |
| dc.contributor.author | Chieh-Yun Huang | en |
| dc.contributor.author | 黃捷允 | zh_TW |
| dc.date.accessioned | 2021-06-16T10:19:44Z | - |
| dc.date.available | 2013-08-20 | |
| dc.date.copyright | 2013-08-20 | |
| dc.date.issued | 2013 | |
| dc.date.submitted | 2013-08-16 | |
| dc.identifier.citation | [1] 呂信宏，工業電腦主機板高速訊號線訊號完整度分析與等化器設計，國立臺灣大學碩士論文，2011年6月。
[2] International Technology Roadmap for Semiconductors. London, U. K. [Online]. Available: http://www.itrs.net/ [3] C.-T. Wu and R.-B. Wu, “Two-dimensional finite-difference time-domain method combined with open boundary for signal integrity issues between isolation islands,” in IEEE 11th Electrical Performance Eletron. Packag., Monterey, California, USA, Oct. 21–23, 2002, pp. 283–286. [4] C.-L. Wang, G.-H. Shiue, and R.-B. Wu, “EBG-enhanced split power planes for wideband noise suppression,” in IEEE 14th Electrical Performance Electron. Packag., Austin, Texas, USA, Oct. 24–26, 2005, pp. 61–64 [5] K.-B. Wu, R.-B. Wu, and Daniel De Zutter, “Modeling and optimal design of shorting vias to suppress radiated emission in high-speed alternating PCB planes,” IEEE Trans. Comp., Packag., Manuf. Technol., vol. 1, no. 4, pp. 566–573, April 2011. [6] K.-B. Wu, G.-H. Shiue, W.-D. Guo, C.-M. Lin, and R.-B. Wu, “Delaunay-Voronoi modeling of power-ground planes with source port correction,” IEEE Trans. Adv. Packag., vol. 31, no. 2, pp. 303–310, May 2008. [7] J. M. Hobbs, H. Windlass, V. Sundaram, S. Chun, G. E. White, M. Swaminathan, and R. R. Tummalas, “Simultaneous switching noise suppression for high speed systems using embedded decoupling,” in Proc. 51st Electron. Comp. Technol. Conf., Orlando, Florida, USA, May 29–June 1, 2001, pp. 339–343. [8] K. Bharath, E. Engin, and M. Swaminathan, “Automatic package and board decoupling capacitor placement using genetic algorithms and M-FDM,” in Proc. 45th IEEE Des. Autom. Conf., 2008, pp. 560–565. [9] S. Kose and E. G. Friedman, “Distributed power network co-design with on-chip power supplies and decoupling capacitors,” in Proc. Workshop Syst. Level Interconnect Prediction, Jun. 2011, pp. 1–5. [10] J. Fan; J. L. Knighten, A. Orlandi, N. W. Smith, J. L. Drewniak, 'Quantifying decoupling capacitor location,' IEEE Electromagn. Compat. Internation. Symp., vol. 2, pp.761 – 766 , Aug. 2000. [11] A. Waizman, O. Vikinski, and G. Sizikov, “CPU power devilery impedance profile resonances impact on core FMAX,” IEEE Electr. Perform. Electron. Packag., pp.119,122, Oct. 2006 [12] 李冠緯，利用去耦合電容抑制電源接地平面板邊輻射雜訊之分析與設計，國立臺灣大學碩士論文，2011年6月。 [13] L. D. Smith, R. E. Anderson, D. W. Forehand, T. J. Pelc, and T. Roy, “Power distribution system design methodology and capacitor selection for modern CMOS technology,” IEEE Trans. Adv. Packag., vol. 22, no. 3, pp. 284–291, Aug. 1999. [14] L.D. Smith, D. Hockanson, “Distributed SPICE Circuit Model for Ceramic Capacitors,” in Proc. IEEE Electron. Components Technol. Conf., May/Jun. 2001, pp. 523 – 528. [15] M. Swaminathan and A. E. Engin, Power Integrity Modeling and Design for Semiconductors and System, Ch. 1, Prentice Hall, 2007. [16] M. Swaminathan, J. Kim, I. Novak, and J. P. Libous, “Power distribution networks for system-on-package: status and challenges,” IEEE Trans. Adv. Packag., vol. 27, no. 2, pp. 286–300, May 2004. [17] D. Soldo and S. G. Pytel Jr., “Automated decoupling capacitor analysis for analog/digital printed circuit boards,” in 8th Workshop Electromagn. Compat. Integ. Circuits, Dubrovnik, Croatia, Nov. 6–9, 2011, pp. 111–114. [18] 徐志榮，針對高速記憶體輸入/輸出介面之信號/電源完整性晶片－封裝共模擬分析與設計，國立臺灣大學碩士論文，2010年6月。 [19] P. Du, X. Hu, S.-H. Weng, A. Shayan, X. Chen, A. E. Engin, and C.-K. Cheng, “Worst-case noise prediction with non-zero current transition times for early power distribution system verification,” in IEEE Int’l. Symp. Quality Electron. Design, San Jose, California, USA, Mar. 22–24, 2010, pp. 624–631. [20] X. Hu, W. Zhao, P. Du, Y. Zhang, A. Shayan, C. Pan, A. E. Egin, and C.-K. Cheng, “On the bound of time-domain power supply noise based on frequency-domain target impedance,” in ACM/IEEE Workshop System Level Interconnect Prediction, San Francisco, California, USA, July 26–27, 2009, pp. 69–76. [21] E. H.-K. Hsiung, Y.-L. Li, R.-B. Wu, T. Su, Y.-S. Cheng, and K.-B. Wu, “A linear 4-element model of VRM ---Characteristics, practical uses and limitations,” in IEEE Electrical Design Adv. Packag. Syst. Symp., Dec. 9–11, 2012, pp. 13–16. [22] T. H. Hubing, J. L. Drewniak, T. P. Van Doren, and D. M. Hockanson, “Power bus decoupling on multilayer printed circuit boards,” IEEE Trans. Electromagn. Compat., vol. 37, pp. 155–166, May 1995. [23] PI Advisor (Version 5.0.0, Ansys, Inc.)[Online] Available: www.ansys.com) | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/60495 | - |
| dc.description.abstract | 本論文提出集總節點分析法的方法，以分析設計一個系統的電源完整性。近年來，印刷電路板的設計變得越來越複雜，電源供應網路的輸入阻抗也變得越來越低。一般來說，去耦合電容可以被應用於降低電源供應網路的輸入阻抗然而在目前的工業電腦當中，有許多不需要的去耦合電容被使用，不僅僅會造成設計上的困難，而且也會也增加設計的成本，以及印刷電路板當中的使用的面積。
因此，本論文提出了一個新的集總節點分析法，進行去耦合電容的最佳化，並實際應用於目前的高速數位系統。不僅僅改善印刷電路板的輸入阻抗，也減少了去耦合電容的數量。 本文將詳細介紹其原理以及流程，並進行模擬以及實驗比較，證實本法的正確性。 | zh_TW |
| dc.description.abstract | This thesis presents a simple method to analyze and optimize the power integrity of high-speed digital systems. Modern PCB (print circuit board) design becomes more complex, since target impedance of the PDN (power distribution network) is getting lower in recent years. The decoupling capacitors can be used to maintain the impedance, but sometimes there are a lot of unnecessary decoupling capacitors, leading to increased design difficulty, cost, and PCB size.
A simple optimization method based on a called lumped node analysis is proposed to deal with decoupling capacitors design. The analysis can reduce the number of decoupling capacitors with better input impedance. Both simulation and experimental results are presented to validate the method. Besides, the design flow and the theory are also discussed in detail. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-16T10:19:44Z (GMT). No. of bitstreams: 1 ntu-102-R00942084-1.pdf: 2647854 bytes, checksum: a735a79bba7cb4f4a6ef17444e28ab95 (MD5) Previous issue date: 2013 | en |
| dc.description.tableofcontents | 口試委員審定書 i
誌謝…………………. ii 中文摘要……………. ……….…………………………………….iii Abstract…………….. iv 目錄………………… v 圖目錄………… vii 表目錄………….. xi Chapter 1 緒論 1 1.1 研究動機 1 1.2 文獻探討 2 1.3 章節內容概述 8 Chapter 2 理論 9 2.1 單節點分析法 9 2.2 電源分佈網路之低頻等效電路 12 Chapter 3 去耦合電容最佳化擺置設計 17 3.1 反共振點 17 3.2 去耦合電容最佳化設計流程 22 3.3 設計流程概述 31 Chapter 4 去耦合電容擺置實際應用 34 4.1 應用於工業電腦主機板 34 4.2 時域模型與驗證 39 4.3 與模擬軟體 PI Advisor 之比較 42 4.4 應用於工業電腦主機板之不同目標阻抗設計 52 Chapter 5 實驗驗證與結論 57 參考文獻…………… 61 | |
| dc.language.iso | zh-TW | |
| dc.subject | 電源供應網路 | zh_TW |
| dc.subject | 電源完整性 | zh_TW |
| dc.subject | 去耦合電容 | zh_TW |
| dc.subject | power distribution network | en |
| dc.subject | power integrity | en |
| dc.subject | Decoupling capacitor | en |
| dc.title | 利用集總節點分析電源完整性與去耦合電容最佳化擺置 | zh_TW |
| dc.title | Decoupling Capacitor Optimization for Power Integrity Using Lumped Node Analysis | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 101-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 張康維(Kang-Wei Chang),林建民,吳宗霖 | |
| dc.subject.keyword | 電源完整性,去耦合電容,電源供應網路, | zh_TW |
| dc.subject.keyword | Decoupling capacitor,power distribution network,power integrity, | en |
| dc.relation.page | 64 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2013-08-16 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電信工程學研究所 | zh_TW |
| 顯示於系所單位： | 電信工程學研究所 | |
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| ntu-102-1.pdf 未授權公開取用 | 2.59 MB | Adobe PDF |
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