利用圓柱函數基底萃取直通矽晶穿孔柱陣列之電氣參數

Abstract

著名的摩爾定律(Moore’s law)指出，積體電路(IC)中的電晶體每隔約兩年將會加倍。但在現今(2013)的半導體產業界中，由於各種困難，使得我們逐漸難以繼續遵守此定律。 因此，為了跟上摩爾定律，許多新方法被提出來取代舊有的方式：藉由縮小電晶體來達成電晶體密度的增加與功耗降低。其中一種廣為人知的方式為藉由垂直堆疊多層積體電路的三維積體電路(3D IC)。 在三維積體電路(3D IC)中，直通矽晶連通柱(TSV)作為積體電路之間的垂直信號與電源連結。然而，高達每平方公分105至107根互相平行直通矽晶連通柱、和半導體的基體特性，使得等效電路模型的萃取及模擬是非常耗時的工作。 本論文利用圓柱型特性與調和基底函數的關係，提出一個新的等效電路模型萃取方法，並同時考慮半導體與電磁效應。此一新方法充分利用直通矽晶連通柱其為圓柱之形狀，在維持良好的準確度的前提下，提高計算的效能。

In the modern semiconductor industry, it has become harder to keep following Moore’s law, which states that the number of transistors in Integrated Circuit (IC) doubles approximately every two years. Thus, instead of just shrinking the device, several other ways have been proposed to keep up with Moore’s law. Three-dimensional Integrated Circuit (3D IC) has provided a solution by vertically stacking the multiple ICs and thus increased the density of transistors without shrinking it. Within this technology, Through-Silicon Vias (TSVs) are formed in each IC in order to connect the signals vertically. However, because of the typical high density of 105 ~ 107 per cm2, the vertical parallel nature in geometry, and the coupling properties of semiconductor substrate, the equivalent model extraction and performance analysis for TSVs have become time consuming. This thesis proposes a new extraction method, while including the semiconductor effect, to accelerate the construction of equivalent model with the cylindrical basis, taking advantage of the cylindrical nature of TSVs, while remaining a good accuracy.