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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 吳瑞北(Ruey-Beei Wu) | |
| dc.contributor.author | Chang-Bao Chang | en |
| dc.contributor.author | 張長葆 | zh_TW |
| dc.date.accessioned | 2021-06-16T10:19:35Z | - |
| dc.date.available | 2013-11-05 | |
| dc.date.copyright | 2013-11-05 | |
| dc.date.issued | 2013 | |
| dc.date.submitted | 2013-08-16 | |
| dc.identifier.citation | [1] “International Technology Roadmap for Semiconductors.” [Online]. Available: http://www.itrs.net/Links/2012ITRS/Home2012.htm.
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/60490 | - |
| dc.description.abstract | 著名的摩爾定律(Moore’s law)指出，積體電路(IC)中的電晶體每隔約兩年將會加倍。但在現今(2013)的半導體產業界中，由於各種困難，使得我們逐漸難以繼續遵守此定律。
因此，為了跟上摩爾定律，許多新方法被提出來取代舊有的方式：藉由縮小電晶體來達成電晶體密度的增加與功耗降低。其中一種廣為人知的方式為藉由垂直堆疊多層積體電路的三維積體電路(3D IC)。 在三維積體電路(3D IC)中，直通矽晶連通柱(TSV)作為積體電路之間的垂直信號與電源連結。然而，高達每平方公分105至107根互相平行直通矽晶連通柱、和半導體的基體特性，使得等效電路模型的萃取及模擬是非常耗時的工作。 本論文利用圓柱型特性與調和基底函數的關係，提出一個新的等效電路模型萃取方法，並同時考慮半導體與電磁效應。此一新方法充分利用直通矽晶連通柱其為圓柱之形狀，在維持良好的準確度的前提下，提高計算的效能。 | zh_TW |
| dc.description.abstract | In the modern semiconductor industry, it has become harder to keep following Moore’s law, which states that the number of transistors in Integrated Circuit (IC) doubles approximately every two years. Thus, instead of just shrinking the device, several other ways have been proposed to keep up with Moore’s law. Three-dimensional Integrated Circuit (3D IC) has provided a solution by vertically stacking the multiple ICs and thus increased the density of transistors without shrinking it. Within this technology, Through-Silicon Vias (TSVs) are formed in each IC in order to connect the signals vertically. However, because of the typical high density of 105 ~ 107 per cm2, the vertical parallel nature in geometry, and the coupling properties of semiconductor substrate, the equivalent model extraction and performance analysis for TSVs have become time consuming.
This thesis proposes a new extraction method, while including the semiconductor effect, to accelerate the construction of equivalent model with the cylindrical basis, taking advantage of the cylindrical nature of TSVs, while remaining a good accuracy. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-16T10:19:35Z (GMT). No. of bitstreams: 1 ntu-102-R00942126-1.pdf: 5578760 bytes, checksum: 9c35e3847542f78e5645d6822245e508 (MD5) Previous issue date: 2013 | en |
| dc.description.tableofcontents | 誌謝 i
中文摘要 iii Abstract v Contents vii List of Tables xi List of Figures xiii Chapter 1 Introduction 1 1.1 Three Dimensional System Integration 1 1.1.1 Through Silicon Interconnection 1 1.1.2 Stacking Strategy 3 1.1.3 Modeling Challenge 4 1.2 Contribution 5 1.3 Thesis Outline 5 Chapter 2 Basic Theory and Assumptions 7 2.1 Basic Electromagnetism 7 2.1.1 Auxiliary Variables and Green’s Theorem 7 2.1.2 Integral Equation 10 2.2 Previous Work 11 2.2.1 Electromagnetic Aspect 11 2.2.2 Semiconductor Aspect 13 2.3 Assumption Used in this Thesis 14 2.3.1 Quasi-Static Field Approximation 14 2.3.2 Decoupling of Electric and Magnetic Field 16 2.3.3 Drift Diffusion Model (DDM) 16 2.3.4 Neglection of Hall Effect inside Silicon 17 2.3.5 Summary 17 Chapter 3 Inductance and Resistance Extractions of Through Silicon Vias 19 3.1 Introduction 19 3.1.1 Magnetic Induced Effect 19 3.1.2 Modeling Challenges 21 3.2 Decoupling of Electric and Magnetic Field 22 3.3 Partial Element Equivalent Circuit (PEEC) 23 3.3.1 Extraction of Inductance and Resistance 23 3.4 Basis Function 24 3.4.1 Conduction Model Basis Function (CMBF) 24 3.4.2 Frequency Independent Cylindrical basis Function 26 3.4.3 Green’s Function in Cylindrical Coordinate 29 3.4.4 Equivalent Circuit 30 3.4.5 Method of Integration 31 3.4.6 Current Density 33 3.4.7 Convergence 33 3.5 Validation and Comparison 35 3.5.1 Several Previous Technique in Inductance Extraction 35 3.5.2 Several Previous Technique in Resistance Extraction 37 3.5.3 Comparison of Different Method 38 3.6 Summary 48 Chapter 4 Capacitance and Conductance Extractions of Through Silicon Via 49 4.1 Aspects of Modeling 49 4.1.1 Electromagnetic Aspect 49 4.1.2 Semiconductor Aspect 50 4.2 Biased and Unbiased Substrate 58 4.2.1 Biased Substrate 58 4.2.2 Unbiased Substrate 59 4.3 Conventional Model 61 4.4 Cylindrical Cylindrical basis 65 4.4.1 Simple Layer Boundary Element Method 65 4.4.2 Cylindrical basis 66 4.5 Validation and Comparison 70 4.5.1 Several Previous Technique in Capacitance extraction 70 4.5.2 . Comparison of Different Method 70 4.6 Summary 71 Chapter 5 Future Works and Conclusions 73 5.1 Future Works 73 5.1.1 Inductance Modeling 73 5.1.2 Capacitance Modeling 73 5.2 Conclusions 75 Reference 77 | |
| dc.language.iso | en | |
| dc.title | 利用圓柱函數基底萃取直通矽晶穿孔柱陣列之電氣參數 | zh_TW |
| dc.title | Extraction of Electrical Parameters of Through Silicon Vias Using Cylindrical Basis | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 101-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 楊明宗,吳宗霖,林建民,洪子聖 | |
| dc.subject.keyword | 三維積體電路,直通矽晶穿孔柱,矩量法,邊界元素法,圓柱函數,部分元件等效電路, | zh_TW |
| dc.subject.keyword | Three-dimensional integrated circuit,through silicon via,moment method,boundary element method,cylindrical function,partial element equivalent circuit, | en |
| dc.relation.page | 82 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2013-08-16 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電信工程學研究所 | zh_TW |
| 顯示於系所單位： | 電信工程學研究所 | |
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