基於現場可程式邏輯陣列的低成本次奈秒時序格式產生器

Abstract

時序格式產生器為半導體自動測試設備(ATE)的關鍵元件之一，目前市面上達到奈秒以下解析度的自動測試設備皆以ASIC或Analog Devices的ADATE207做為時序格式產生器，尚無使用現場可程式化邏輯陣列(FPGA)實現的次奈秒時序格式產生器。FPGA有低設計成本、高設計靈活度與快速的上市時間等優點，如果以FPGA實現時序格式產生器將享有這些優勢。 在本論文中，以Altera Cyclone II FPGA實現時序格式產生器，提出的時序格式產生器主要由Wishbone匯流排、時間分工技術的符號產生器、基於FPGA的混合式延遲線與內建自我測試和校正電路組成。其中最重要的部分是延遲線，為了於FPGA上實做延遲線，我們提出針對FPGA內部架構開發的延遲線、與延遲線EDA工具。 結合這些技術後，時序格式產生器測試符號速率達到100Mhz，時間解析度20ps，時間精確度74ps，並支援RZ、RO、NRZ、DNRZ和SBC等訊號格式，與圖形化控制介面。

Timing generator and formatter are both the key building blocks for the automatic test equipment (ATE). Nowadays, for ATEs to achieve sub-nanosecond timing accuracy, timing generator and formatter are typically implemented by the dedicated ASIC (Application-Specific Integrated Circuit) or ADATE207 from Analog Devices Inc., whereas implementations with FPGA have not yet been seen. Compared to ASIC, FPGAs have distinct advantages such as lower cost, higher design flexibility, and shorter time to market. ATE could also benefit from the above mentioned advantages if the timing generator and formatter are realized by the FPGA. In this thesis, an Altera Cyclone II FPGA development board is utilized to implement the timing generator and formatter. The proposed system consists of Wishbone Bus, time-interleaved symbol generator, FPGA-based delay line, and built-in self-test calibration circuits. To realize the FPGA-based delay lines, we investigate the cell architecture of the FPGA and develop EDA tools to synthesis delay lines using primitive FPGA cells. Experimental results show that, 100 Mhz test rate, 20 ps timing resolution and 74 ps timing accuracy are achieved while supporting signal formats such as RZ (Return to Zero), RO (Return to One), NRZ (Non Return to Zero), DNRZ (Delayed Non Return to Zero), and SBC (Surround by Compliment). Furthermore, a graphical user interface is implemented.