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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 黃俊郎 | |
dc.contributor.author | Yu-Yi Chen | en |
dc.contributor.author | 陳宇奕 | zh_TW |
dc.date.accessioned | 2021-06-16T10:13:36Z | - |
dc.date.available | 2018-09-06 | |
dc.date.copyright | 2013-09-06 | |
dc.date.issued | 2013 | |
dc.date.submitted | 2013-08-20 | |
dc.identifier.citation | [1] Automated Test Outlook 2013. National Instruments, 2013.
[2] The Fundamentals of Digital Semiconductor Testing. Soft Test, 2013. [3] Wang, L.T., Stround, C.E., Touba, and Nur A. System-on-Chip Test Architectures: Nanometer Design for Testability. Morgan Kaufmann, 2007. [4] Wang, L.T., Wu, C.W., and Wen X., VLSI Test Principles and Architectures: Design for Testability. Morgan Kaufmann, 2006. [5] Mostardini, Luca, et al. 'FPGA-based low-cost automatic test equipment for digital integrated circuits.' IEEE International Workshop on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications, 2009. [6] Syed, Ahmed Rashid, and Staff Design Engineer. 'RIC/DICMOS-Multi-channel CMOS Formatter.' IEEE International Test Conference. 2003. [7] Park, Jaeseok, et al. 'Integration of dual channel timing formatter system for high speed memory test equipment.' IEEE SoC Design Conference (ISOCC), 2012. [8] ADATE207 Quad Pin Timing Formatter Data Sheet. Analog Device, 2007. [9] J. Li, Z. Zheng, M. Liu, and S. Wu. Large dynamic range accurate digitally programmable delay line with 250-ps resolution. Proceedings of International Conference on Signal Processing (ISCP), 2006. [10] C. Lin, B. Shao, and J. Zhang. A multi-channel digital programmable delay trigger system with high accuracy and wide range. Proceedings of International Conference on Electronics, Communications and Control (ICECC), pages 1835–1838, 2011. [11] Virtex-6 FPGA SelectIO Resources. Xilinx, 2013. [12] Altera Website [Online]. Available: http://www.altera.com/ [13] Xilinx Website [Online]. Available: http://www.xilinx.com/ [14] Wu, Jinyuan, and Zonghan Shi. 'The 10-ps wave union TDC: Improving FPGA TDC resolution beyond its cell delay.' IEEE Nuclear Science Symposium Conference Record, 2008. [15] WISHBONE System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores. OpenCores, 2010. [16] Designing with Low-Level Primitives. Altera, 2007. [17] LCELL WYSIWYG Description for the Cyclone II Architecture. Altera, 2005. [18] Majzoobi, M., Koushanfar, F., and Devadas, S. FPGA PUF using programmable delay lines. IEEE International Workshop on In Information Forensics and Security. IEEE, 2010 | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/60203 | - |
dc.description.abstract | 時序格式產生器為半導體自動測試設備(ATE)的關鍵元件之一,目前市面上達到奈秒以下解析度的自動測試設備皆以ASIC或Analog Devices的ADATE207做為時序格式產生器,尚無使用現場可程式化邏輯陣列(FPGA)實現的次奈秒時序格式產生器。FPGA有低設計成本、高設計靈活度與快速的上市時間等優點,如果以FPGA實現時序格式產生器將享有這些優勢。
在本論文中,以Altera Cyclone II FPGA實現時序格式產生器,提出的時序格式產生器主要由Wishbone匯流排、時間分工技術的符號產生器、基於FPGA的混合式延遲線與內建自我測試和校正電路組成。其中最重要的部分是延遲線,為了於FPGA上實做延遲線,我們提出針對FPGA內部架構開發的延遲線、與延遲線EDA工具。 結合這些技術後,時序格式產生器測試符號速率達到100Mhz,時間解析度20ps,時間精確度74ps,並支援RZ、RO、NRZ、DNRZ和SBC等訊號格式,與圖形化控制介面。 | zh_TW |
dc.description.abstract | Timing generator and formatter are both the key building blocks for the automatic test equipment (ATE). Nowadays, for ATEs to achieve sub-nanosecond timing accuracy, timing generator and formatter are typically implemented by the dedicated ASIC (Application-Specific Integrated Circuit) or ADATE207 from Analog Devices Inc., whereas implementations with FPGA have not yet been seen. Compared to ASIC, FPGAs have distinct advantages such as lower cost, higher design flexibility, and shorter time to market. ATE could also benefit from the above mentioned advantages if the timing generator and formatter are realized by the FPGA.
In this thesis, an Altera Cyclone II FPGA development board is utilized to implement the timing generator and formatter. The proposed system consists of Wishbone Bus, time-interleaved symbol generator, FPGA-based delay line, and built-in self-test calibration circuits. To realize the FPGA-based delay lines, we investigate the cell architecture of the FPGA and develop EDA tools to synthesis delay lines using primitive FPGA cells. Experimental results show that, 100 Mhz test rate, 20 ps timing resolution and 74 ps timing accuracy are achieved while supporting signal formats such as RZ (Return to Zero), RO (Return to One), NRZ (Non Return to Zero), DNRZ (Delayed Non Return to Zero), and SBC (Surround by Compliment). Furthermore, a graphical user interface is implemented. | en |
dc.description.provenance | Made available in DSpace on 2021-06-16T10:13:36Z (GMT). No. of bitstreams: 1 ntu-102-R96943121-1.pdf: 2321755 bytes, checksum: ddf206fab29f8ec97fba44865e60428c (MD5) Previous issue date: 2013 | en |
dc.description.tableofcontents | 口試委員會審定書 i
誌謝 ii 中文摘要 iii ABSTRACT iv 目錄 v 圖目錄 viii 表目錄 x 第1章 緒論 1 1.1 研究動機與目的 1 1.2 重要貢獻 2 1.3 論文架構 3 第2章 時序格式產生器之挑戰與相關研究 4 2.1 半導體自動測試設備(ATE) 4 2.2 時序格式產生器(Timing Generator and Formatter) 5 2.3 數位可程式化延遲線 (Digital Programmable Delay Line) 8 2.4 現場可程式化邏輯陣列 (Field-Programmable Gate Array) 9 第3章 基於FPGA之時序格式產生器 12 3.1 系統架構 12 3.2 時序格式產生器架構設計 13 3.3 延遲線控制時序與需求規格分析 18 3.4 內建自我測試與校正 23 3.4.1 起始點偏移測試與校正 23 3.4.2 非線性誤差測試與校正 26 第4章 基於FPGA之延遲線 31 4.1 延遲線架構 31 4.1.1 Block-box Delay Line 31 4.1.2 LAB-based Carry Chain Delay Line 32 4.1.3 LUT-based Vernier Delay Line 33 4.1.4 混合式延遲線 36 4.2 延遲線實作技術 36 4.2.1 低階原始物件(Low-Level Primitives) 38 4.2.2 位置指定(Location Assignment) 39 4.2.3 連接埠與繞線路徑指定(Port and Routing Assignment) 39 4.2.4 LUT-based Delay Cell合成技術 40 第5章 實驗結果 41 5.1 設計目標規格與實做結果 41 5.2 量測配置 42 5.3 延遲線實現結果 43 5.3.1 延遲線量測結果 43 5.3.2 偏移校正結果 46 5.3.3 INL與DNL校正結果 47 5.3.4 混合式延遲線組合結果 48 5.4 圖形化使用者介面 (GUI) 50 5.5 邊緣置放(Edge Placement)與任意波形產生範例 51 第6章 結論與未來研究方向 53 6.1 結論 53 6.2 未來研究方向 55 參考文獻 56 | |
dc.language.iso | zh-TW | |
dc.title | 基於現場可程式邏輯陣列的低成本次奈秒時序格式產生器 | zh_TW |
dc.title | An FPGA-based Sub-nanosecond Low-cost Timing Generator and Formatter | en |
dc.type | Thesis | |
dc.date.schoolyear | 101-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 鄭國興,李建模,黃炫倫 | |
dc.subject.keyword | 自動化測試設備,時序格式產生器,延遲線,現場可程式化邏輯陣列, | zh_TW |
dc.subject.keyword | Automatic Test Equipment,Timing Generator,Timing Formatter,Delay Line,FPGA, | en |
dc.relation.page | 57 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2013-08-20 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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