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標題: | 具高能源效率寬操作範圍之靜態隨機存取記憶體設計與實現 Design and Implementation of an Energy-Efficient Wide-Operating-Range SRAM |
作者: | Ya-Ting Yang 楊雅婷 |
指導教授: | 闕志達(Tzi-Dar Chiueh) |
關鍵字: | 靜態隨機存取記憶體,寬廣操作範圍,低電壓記憶體,低耗電,高效能, SRAM,wide-operating range,low-voltage memory,low power consumption,high performance, |
出版年 : | 2013 |
學位: | 碩士 |
摘要: | 嵌入式記憶體在現今高效能低功耗晶片中有很重要的地位,隨著資料需求量的上升,佔據了處理器相當大比例的面積與功率消耗,如果能針對記憶體這部分進行設計,提供高能源效率、低功耗及低電壓操作的記憶體,即可以大幅度減少處理器的整體功率消耗。在許多的半導體記憶體技術中,靜態隨機存取記憶體因為具有高速及低功耗的優點,更是扮演著不可或缺的角色。
本論文提出一具有寬廣操作範圍的靜態隨機存取記憶體,使用TSMC TN40G的製程工作,電壓範圍為0.35v~0.9v,能根據性能要求來調節系統供應電壓源,可操作於低電壓下幫助降低整體晶片的功率消耗,也可工作於較高電壓達到效能上的需求。此一靜態隨機存取記憶體使用合併資料線的八電晶體靜態記憶細胞元,並且利用階層式架構的讀寫資料線以降低負載和增加讀寫速度。利用可隨著工作電壓動態調整的爆發式讀寫字元線技術(adaptive boosting WL/RWL),增加記憶體的讀取與寫入能力;同時也提出隨著工作電壓動態調整的低擺幅讀取資料線技術(adaptive low-swing RBL),減少讀取時的功率消耗與降低讀取延遲。在對抗製程變異的設計技巧上,虛擬記憶體控制單元(dummy row/column control)可有效的模擬全域性製程變異所帶來的影響。而對於減緩區域性製程變異所帶來的影響,則是提出了區域性額外爆發式讀寫字元線技術(extra-boosting WL/RWL),針對特定記憶體區塊提供更高電位的爆發式字元線。利用上述所提到的架構,我們完成一個具有寬廣操作範圍、高效能與高能源效益的64Kb靜態隨機存取記憶體。 Embedded memories take an important place in today high-performance and low-power computing ICs. Along with the rapid growth of data requirement, memories can occupy the majority of the chip area and power consumption. This dominance forces designers to design high-density and low-power memories, which is the most effective way to reduce the overall power consumption of ICs. Static Random Access Memories (SRAM) have the advantage of high-speed and low-power operation, play an indispensable role in embedded memories. In this thesis, we propose a 40nm wide-operating range SRAM, which can operate between 0.35v ~ 0.9v. The proposed SRAM can be operated at low voltage point to help reducing the power consumption and higher voltage range to meet the performance requirement. The SRAM’s power supply can be adjusted according to user’ needs. We use 8T SRAM cell with merged BLB/RBL as our memory cell and optimize the size to have a better stability in low-voltage range. In SRAM structure, we apply hierarchical BL/RBL to reduce the bit-lines’ loading and write/read access time. In peripheral circuit design, adaptive WL/RWL boosting skills are used to enhance the write and read ability. Adaptive low-swing RBL skill is also used to reduce the read access time and power. In order to tolerant process variation, dummy row/column timing control unit is applied to mimic the influence of global process variation, while extra WL/RWL boosting is applied to diminish the error probability cause by the local process variation. With the help of above techniques, we fabricate a wide-operating range, high-performance and energy-efficient 64Kb SRAM. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/58847 |
全文授權: | 有償授權 |
顯示於系所單位: | 電子工程學研究所 |
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