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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 闕志達(Tzi-Dar Chiueh) | |
dc.contributor.author | Ya-Ting Yang | en |
dc.contributor.author | 楊雅婷 | zh_TW |
dc.date.accessioned | 2021-06-16T08:34:28Z | - |
dc.date.available | 2019-01-27 | |
dc.date.copyright | 2014-01-27 | |
dc.date.issued | 2013 | |
dc.date.submitted | 2013-11-29 | |
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Chandrakasan, “A 512kb 8T SRAM macro operating down to 0.57V with an AC-coupled sense amplifier and embedded data-retention-voltage sensor in 45nm SOI CMOS,” in Proc. IEEE Int. Soid-State Circuits Conf., Feb. 2010, pp. 350–351. [19] Y. W. Lin, H. I Yang, G. C. Lin, C. C. Chang, C. T. Chuqng, W. Hwang, C. C. Chen, W. Shih and H. S. Huang, “A 55nm 0.55V 6T SRAM with variation-tolerant dual-tracking word-line under-drive and data-aware write-assist,” IEEE Int. Symp. Low Power Electronics and Design (ISLPED), Jul. 2012, pp. 79–84. [20] S. Miyano, S. Moriwaki, Y. Yamamoto, A. Kawasumi, T. Suzuki, T. Sakurai and H. Shinohara, “Highly energy-efficient SRAM with hierarchical bit line charge-sharing method using non-selected bit line charges,” IEEE Journal of Solid-State Circuits, vol. 48, no. 4, pp. 924–931, Apr. 2013. [21] C. H. Tsai, “Ultra Low Voltage And Low Leakage Delay Buffer Circuit Design,” National Taiwan University master thesis, Jan. 2012. [22] A. Raychowdhury, B. Geuskens, J. Kulkarni, J. Tschanz, K. Bowman, T. Karnik, S. L. Lu, V. D., M. M. Khellah, “PVT-and-aging adaptive wordline boosting for 8T SRAM powerreduction,” in Proc. IEEE Int. Soid-State Circuits Conf., Feb. 2010. pp. 352–353. [23] M. F. Chang, S. W. Chang, P. W. Chou, and W. C. Wu, “A 130 mV SRAM with expanded write and read margins for subthreshold applications,” IEEE Journal of Solid-State Circuits, vol. 46, no. 2, pp. 520–529, Feb. 2011. [24] A. P. Chandrakasan, D. C. Daly, D. F. Finchelstein, J. Kwong, and Y. K. Ramadass, “Technologies for ultradynamic voltage scaling,” Proc. of the IEEE, vol. 98, no. 2, Feb. 2010, pp. 191–214. [25] J. P. Kulkarni, K. Keejong and K. Roy, “A 160 mV robust Schmitt trigger based subthreshold SRAM,” IEEE Journal of Solid-State Circuits, vol. 42, no. 10, pp. 2303–2313, Feb. 2007. [26] J. C. Ik, J. J. Kim, S. P. Park and K. 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Huang, “P-P-N Based 10T SRAM Cell for Low-Leakage and Resiliant subthreshold operation,” IEEE Journal of Solid-State Circuits, vol. 46, no. 3, pp. 695–704, Feb. 2011. [30] M. H. Tu, J. Y. Lin, M. C. Tsai, C. Y. Lu, Y. J. Lin, M. H. Wang, H. S. Huwang, K. D. Lee, W. C. Shih, S. J. Jou and C. T. Chuang, “A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing,” IEEE Journal of Solid-State Circuits, vol. 47, no. 6, pp. 1469–1482, Apr. 2012. [31] S. M. Yang, M. F. Chang, K. T. Chen, W. C. Wu, Y. H. Chou, T. S. Chao, M. B. Chen and P. C. Chen, “Wide VDD Embedded Asynchronous SRAM With Dual-Mode Self-Timed Technique for Dynamic Voltage Systems,” Memory Tech., Design, and Testing (MTDT), Aug. 2009, pp. 20–24. [32] A. Raychowdhury, B. M. Geuskens, K. A. Bowman, J. W. Tschanz, S. L. Lu, T. Karnik, M. M. Khellah and V. K. De, “Tunable replica bits for dynamic variation tolerance in 8T SRAM arrays,” IEEE Journal of Solid-State Circuits, vol. 46, no. 4, pp. 797–805, Mar. 2011. [33] S. Lutkemeier, T. Jungeblut, H. K. O. Berge, S. Aunet, M. Porrmann and U. Ruckert, “A 65nm 32 b subthreshold processor with 9T multi-Vt SRAM and adaptive supply voltage control,” IEEE Journal of Solid-State Circuits, vol. 48, no.1, pp. 8–19, Jan. 2013. [34] Y. H. Chen, S. Y. Chou, Q. Li, W. M. Chan, D. Sun, H. J. Liao, P. Wang, M. F. Chang and H. Yamauchi, “Compact measurement schemes for BL swing, SA offset voltage, and WL pulse width to characterize sensing tolerance margin in a 40nm fully functional embedded SRAM,” IEEE Journal of Solid-State Circuits, vol. 47, no.4, pp.9698–980, Apr. 2012. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/58847 | - |
dc.description.abstract | 嵌入式記憶體在現今高效能低功耗晶片中有很重要的地位,隨著資料需求量的上升,佔據了處理器相當大比例的面積與功率消耗,如果能針對記憶體這部分進行設計,提供高能源效率、低功耗及低電壓操作的記憶體,即可以大幅度減少處理器的整體功率消耗。在許多的半導體記憶體技術中,靜態隨機存取記憶體因為具有高速及低功耗的優點,更是扮演著不可或缺的角色。
本論文提出一具有寬廣操作範圍的靜態隨機存取記憶體,使用TSMC TN40G的製程工作,電壓範圍為0.35v~0.9v,能根據性能要求來調節系統供應電壓源,可操作於低電壓下幫助降低整體晶片的功率消耗,也可工作於較高電壓達到效能上的需求。此一靜態隨機存取記憶體使用合併資料線的八電晶體靜態記憶細胞元,並且利用階層式架構的讀寫資料線以降低負載和增加讀寫速度。利用可隨著工作電壓動態調整的爆發式讀寫字元線技術(adaptive boosting WL/RWL),增加記憶體的讀取與寫入能力;同時也提出隨著工作電壓動態調整的低擺幅讀取資料線技術(adaptive low-swing RBL),減少讀取時的功率消耗與降低讀取延遲。在對抗製程變異的設計技巧上,虛擬記憶體控制單元(dummy row/column control)可有效的模擬全域性製程變異所帶來的影響。而對於減緩區域性製程變異所帶來的影響,則是提出了區域性額外爆發式讀寫字元線技術(extra-boosting WL/RWL),針對特定記憶體區塊提供更高電位的爆發式字元線。利用上述所提到的架構,我們完成一個具有寬廣操作範圍、高效能與高能源效益的64Kb靜態隨機存取記憶體。 | zh_TW |
dc.description.abstract | Embedded memories take an important place in today high-performance and low-power computing ICs. Along with the rapid growth of data requirement, memories can occupy the majority of the chip area and power consumption. This dominance forces designers to design high-density and low-power memories, which is the most effective way to reduce the overall power consumption of ICs. Static Random Access Memories (SRAM) have the advantage of high-speed and low-power operation, play an indispensable role in embedded memories.
In this thesis, we propose a 40nm wide-operating range SRAM, which can operate between 0.35v ~ 0.9v. The proposed SRAM can be operated at low voltage point to help reducing the power consumption and higher voltage range to meet the performance requirement. The SRAM’s power supply can be adjusted according to user’ needs. We use 8T SRAM cell with merged BLB/RBL as our memory cell and optimize the size to have a better stability in low-voltage range. In SRAM structure, we apply hierarchical BL/RBL to reduce the bit-lines’ loading and write/read access time. In peripheral circuit design, adaptive WL/RWL boosting skills are used to enhance the write and read ability. Adaptive low-swing RBL skill is also used to reduce the read access time and power. In order to tolerant process variation, dummy row/column timing control unit is applied to mimic the influence of global process variation, while extra WL/RWL boosting is applied to diminish the error probability cause by the local process variation. With the help of above techniques, we fabricate a wide-operating range, high-performance and energy-efficient 64Kb SRAM. | en |
dc.description.provenance | Made available in DSpace on 2021-06-16T08:34:28Z (GMT). No. of bitstreams: 1 ntu-102-R00943119-1.pdf: 4422491 bytes, checksum: db1422b3cdd4617cc61811cca3474548 (MD5) Previous issue date: 2013 | en |
dc.description.tableofcontents | 誌謝 iii
摘要 v ABSTRACT vii 目錄 ix 圖目錄 xi 表目錄 xiii 第一章 緒論 1 1.1 研究動機 1 1.1.1 寬廣操作範圍系統設計 1 1.1.2 靜態隨機存取記憶體之趨勢與重要性 3 1.2 論文組織介紹 4 第二章 靜態隨機存取記憶體 5 2.1 基本介紹 5 2.1.1 傳統6T記憶體細胞元 5 2.1.2 基本記憶體裝置區塊 6 2.2 細胞元穩定性分析 8 2.2.1 保值與讀取雜訊免疫力 8 2.2.2 寫入能力分析 10 第三章 靜態隨機存取記憶體設計挑戰 12 3.1 低電壓操作設計挑戰 13 3.1.1 電流驅動力的下降 13 3.1.2 漏電流問題 14 3.1.3 穩定性要求 17 3.2 讀取干擾問題 18 3.3 半選取問題 19 3.4 製程變異所帶來影響 20 第四章 寬操作範圍靜態隨機存取記憶體之技術 22 4.1 8T記憶體細胞元 22 4.1.1 操作方式與穩定性分析 22 4.1.2 可變式電壓源與接地端 24 4.2 資料線合併最佳化8T記憶細胞元 25 4.2.1 讀取階段尺寸最佳化 26 4.2.2 保值階段尺寸最佳化 27 4.2.3 寫入階段尺寸最佳化 28 4.3 階層資料位元線架構分析 29 4.4 動態調整低擺幅資料位元線技術 38 4.4.1 合併低擺幅RBL與BLB優點 39 4.5 動態調整爆發式字元線技術 41 4.6 負電壓資料位元線技術 43 4.7 虛擬記憶體時間控制單元 44 4.8 2Kb SRAM十架構間模擬比較 46 第五章 40奈米64Kb靜態隨機存取記憶體之設計與實現 52 5.5 64Kb靜態隨機存取記憶體架構 53 5.6 三階段電源閘式開關 56 5.7 額外區域爆發式字元線技術 57 5.8 實驗模擬結果 60 第六章 電路佈局與晶片量測規劃 66 6.1 電路佈局圖 66 6.1.1 記憶體細胞元與陣列 66 6.1.2 記憶體與周邊電路架構佈局 67 6.1.3 64Kb靜態隨機存取記憶體晶片 69 6.2 佈局後模擬 71 6.3 量測考量 74 6.3.1 數位邏輯位準轉換器 74 6.3.2 量測儀器與測試項目 76 第七章 結論與未來展望 78 參考文獻 79 | |
dc.language.iso | zh-TW | |
dc.title | 具高能源效率寬操作範圍之靜態隨機存取記憶體設計與實現 | zh_TW |
dc.title | Design and Implementation of an Energy-Efficient Wide-Operating-Range SRAM | en |
dc.type | Thesis | |
dc.date.schoolyear | 102-1 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 張孟凡(Meng-Fan Chang),馬席彬(Hsi-Pin Ma) | |
dc.subject.keyword | 靜態隨機存取記憶體,寬廣操作範圍,低電壓記憶體,低耗電,高效能, | zh_TW |
dc.subject.keyword | SRAM,wide-operating range,low-voltage memory,low power consumption,high performance, | en |
dc.relation.page | 83 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2013-11-29 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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