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Title: | 應用於矽中介層三維積體電路封裝之設計方法 Design Methodology for Interposer-Based 3D IC Packaging |
Authors: | Yuan-Kai Ho 何元凱 |
Advisor: | 張耀文 |
Keyword: | 實體設計,逃脫繞線,交錯式針腳陣列,晶片規劃,時鐘樹合成,二點五維積體電路,矽中介層,共同設計, Physical Design,Escape Routing,Staggered Pin Array,Chip Planning,Clock Tree Synthesis,2.5D ICs,Silicon Interposer,Co-design, |
Publication Year : | 2014 |
Degree: | 博士 |
Abstract: | 隨著積體電路封裝技術的演進,設計複雜度也急遽地增加。多種的複雜晶片被整合進單一封裝裡並且使得此封裝的針腳個數也變得非常的多。因此,需考慮封裝外部的針腳排列方式和封裝內部的多晶片整合方式。矽中介層三維積體電路封裝架構被提出來用以解決上述的議題。對於封裝的針腳排列方式,矽中介層三維積體電路封裝常採用交錯式針腳陣列,與傳統的方格式針腳陣列相比,交錯式針腳陣列能夠在相同的面積下容納更多的針腳數目。然而,對於在封裝外部針腳的繞線方法來說,於交錯式針腳陣列的逃脫繞線方法與傳統在方格式針腳陣列的逃脫繞線方法有顯著的不同,無法直接應用既有的方法。另一方面,對於封裝內部的多晶片整合,矽中介層三維積體電路封裝使用被動型矽中介層當作多晶片與封裝基底的連結介面,是先進封裝技術中一個非常被看好的整合方法,晶片彼此間的連線關係可以用晶片等級的金屬線於矽中介層上繞線以增強設計品質。然而,由於多了額外的矽中介層,設計複雜度也急遽地增加。因此,對於先進封裝來說,於封裝外部考慮逃脫繞線演算法和於封裝內部考慮矽中介層和多晶片的共同設計是有必要的。
在本篇論文中,發展了數個演算法去克服所有之前所提到於基於矽中介層的三維堆疊電路封裝的挑戰:(1)封裝外部於交錯式針腳陣列上的逃脫繞線、(2)封裝內部的多晶片和矽中介層的共同設計。 對於交錯式針腳陣列的逃脫繞線,我們首先提出一個單層逃脫繞線演算法。我們先分析交錯式針腳陣列的特性並且提出能夠完全利用交錯式針腳陣列繞線空間的繞線樣式。我們並提出線性規劃和整數線性規劃的方法去完成交錯式針腳陣列的單層逃脫繞線。接著,為了降低製造成本,本篇論文提出了一個多層逃脫繞線演算法去減少使用的繞線層數。我們提出一個選擇逃脫針腳的方法,能夠指派最多的逃脫針腳到目前的金屬層,並且同時能在其他的金屬層上增加可用的繞線空間。我們也將已繞線的針腳所留下的空間考慮進我們的繞線網路中,使得繞線資源能有效地利用。 對於晶片與矽中介層的共同設計,我們首先提出一個整體的規劃演算法去擺置多個晶片於矽中介層上來減少晶片之間的總繞線長度。我們使用一個新的階層式的 B*-tree 來同時擺置多個晶片、巨集元件、和輸入輸出緩衝器,並且使用二部圖匹配演算法去同時建立所有的輸入輸出緩衝器與微凸塊之間的連線關係。此外,我們也發展了一個時鐘樹合成的設計方法來實現晶片與矽中介層共同設計,使用了 N-型的流程去合成一個於矽中介層設計上的完整時鐘樹,我們所提出的流程可以有效地改善時序差異和總繞線長度。 As integrated circuit (IC) packaging technologies advance, the design complexity increases dramatically. Multiple complex chips are integrated into a single package and the pin number of the package is extremely huge. As a result, it is desirable to consider both the arrangement of package pins outside a package and multiple chip integration inside the package. Interposer-based 3D IC packaging is proposed to consider the above issues. For the arrangement of package pins, a staggered pin array is used in interposer-based 3D IC packaging to accommodate a larger package pin number than a grid pin array with the same area. However, the escape routing for staggered pin arrays, which is a key component of routing on the outside of a package, is significantly different from that for grid pin arrays. On the other hand, for chip integration, interposer-based 3D IC packaging introduces a passive silicon interposer as an interface between multiple chips and a package substrate. Inter-chip connections can be routed on the interposer by chip-scale wires to enhance design quality. However, its design complexity increases dramatically due to the extra interposer interface. Consequently, it is desirable to develop escape routing algorithm for the outside of a package and simultaneously consider the co-design of a passive interposer and multiple chips mounted on it for the inside of the package. In this dissertation, several algorithms are developed to conquer all aforementioned interposer-based 3D IC packaging challenges, (1) escape routing on a staggered pin array for the outside of a package, and (2) chip-interposer co-design for the inside of the package. For escape routing on a staggered pin array, we first propose a single-layer escape routing algorithm. We analyze the properties of staggered pin arrays, and propose an orthogonal-side wiring style that fully utilizes the routing resource of the staggered pin array. An LP/ILP based algorithm is presented to solve the staggered-pin-array single-layer escape routing problem. Then, a multilayer escape routing algorithm is also developed to minimize the number of used layers in a staggered pin array for manufacturing cost reduction. We propose an escaped pin selection method to assign a maximal number of escaped pins in the current layer and also to increase useful routing regions for subsequent layers. Missing pins are also modeled in our routing network to utilize the routing resource effectively. For chip-interposer co-design, we first propose a planning algorithm to place multiple chips on an interposer to reduce inter-chip wirelength. A new hierarchical B*-tree is presented to simultaneously place multiple chips, macros, and I/O Buffers. An approach based on bipartite matching is then proposed to concurrently assign signals from I/O buffers to micro bumps. In addition, we also develop a design methodology of clock tree synthesis for chip-interposer co-design. An N-shaped framework is proposed to synthesis a complete tree in interposer-based designs. The proposed framework can effectively improve clock skew and total clock wirelength. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/58671 |
Fulltext Rights: | 有償授權 |
Appears in Collections: | 電子工程學研究所 |
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ntu-103-1.pdf Restricted Access | 3.01 MB | Adobe PDF |
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