具存取行為考量之快閃記憶體位址再映射策略

Abstract

隨著儲存裝置容量的快速成長，設計快閃記憶體管理層之位址投射機制已儼然形成 一個艱鉅的挑戰。另一方面，晶片數目的增加也造成快閃記憶體管理層設計上的困 難。不同於以往針對快取機制優化之設計，我們提出了一個根據存取行為考量所設 計的位置投射機制來進一步利用平行的特性增加效能並且同時減少不必要的資料搬 移所帶來的效能下降。這個機制不只顯著地降低不適當的配置方法所帶來的效能損 耗，並且藉由減少額外寫入提升裝置壽命。最後，藉由一系列之實驗，我們驗證了 所提出方法之有效性，並得到了令人振奮的結果。

Address mapping for flash storage devices has been a challenging design problem for controllers because of the rapidly growing device capacity. On the other hand, the increasing number of chips bring about difficulties in design management of flash storage devices. In contrast to existing address mapping designs that focuses on improving caching mechanism efficiency, we propose a locality-based address remapping strategy to further utilize the parallelism to improve the performance and reduce unnecessary data write imposed by the improper data allocation. The experiments were conducted based on representative realistic workloads to evaluate the efficacy of the proposed scheme. The results reveal that the proposed management can not only improve the performance but also extend the endurance of the flash storage device.