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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
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dc.contributor.advisor | 郭大維(Tei-Wei Kuo) | |
dc.contributor.author | Yu-Cheng Chang | en |
dc.contributor.author | 張育誠 | zh_TW |
dc.date.accessioned | 2021-06-16T06:37:29Z | - |
dc.date.available | 2019-08-01 | |
dc.date.copyright | 2014-08-01 | |
dc.date.issued | 2014 | |
dc.date.submitted | 2014-07-31 | |
dc.identifier.citation | [1] Flash-memory Translation Layer for NAND flash (NFTL). M-Systems, 1998.
[2] A. Ban. Flash File System. US Patent 5,404,485. In M-Systems, April 1995. [3] L.-P. Chang. On Efficient Wear Leveling for Large-scale Flash-memory Storage Systems. In the 2007 ACM symposium on Applied computing (SAC), pages 1126–1130, New York, NY, USA, 2007. ACM. [4] Y.-H. Chang, J.-W. Hsieh, and T.-W. Kuo. Improving flash wear-leveling by proactivelymoving static data. Computers, IEEE Transactions on, 59(1):53–65, Jan 2010. [5] A. Gupta, Y. Kim, and B. Urgaonkar. DFTL: a flash translation layer employing demand-based selective caching of page-level address mappings. In ASPLOS, 2009. [6] JEDEC Solid State Technology Association. Solid-State Drive (SSD) Endurance Workloads, 2012. [7] H. Jo, J.-U. Kang, S.-Y. Park, J.-S. Kim, and J. Lee. FAB: flash-aware buffer management policy for portable media players. IEEE Trans. Consum. Electron., 52(2):485–493, May 2006. [8] M. Jung, E. H. Wilson, and M. Kandemir. Physically Addressed Queueing (PAQ): Improving Parallelism in Solid State Disks. In the IEEE International Symposium on Computer Architecture (ISCA), 2012. [9] H. Kim and S. Ahn. BPLRU: a buffer management scheme for improving random writes in flash storage. In USENIX Conference on File and Storage Technologies (FAST), 2008. [10] J. Kim, J. M. Kim, S. H. Noh, S. L. Min, and Y. Cho. A Space-Efficient Flash Translation Layer For CompactFlash Systems. IEEE Transactions on Consumer Electronics, Nov 2002. [11] S.-W. Lee, D.-J. Park, T.-S. Chung, D.-H. Lee, S. Park, and H.-J. Song. A log buffer-based flash translation layer using fully-associative sector translation. ACM Transactions on Embedded Computing Systems, 6(3), July 2007. [12] Micron. SLC NAND Flash Memory Features MT29F8G08ABACA, 2010. [13] M. Murugan and David.H.C.Du. Rejuvenator: A static wear leveling algorithm for nand flash memory with minimized overhead. In MSST, 2011. [14] D. Park, B. Debnath, and D. Du. CFTL: A Convertible Flash Translation Layer Adaptive to Data Access Patterns. In SIGMETRICS, pages 14–18, June 2010. [15] SpecTek. 64Gib TLC NAND Flash Memory Features FNNB74A, 2011. [16] A. Traeger, E. Zadok, N. Joukov, and C. P. Wright. A Nine Year Study of File System and Storage Benchmarking. Trans. Storage, 4:5:1–5:56, May 2008. [17] C.-H. Wu and T.-W. Kuo. An Adaptive Two-level Management for the Flash Translation Layer in Embedded Systems. In the IEEE/ACM Iinternational Conference on Computer-Aided Design (ICCAD), pages 601–606, New York, NY, USA, 2006. ACM. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/57194 | - |
dc.description.abstract | 隨著儲存裝置容量的快速成長,設計快閃記憶體管理層之位址投射機制已儼然形成
一個艱鉅的挑戰。另一方面,晶片數目的增加也造成快閃記憶體管理層設計上的困 難。不同於以往針對快取機制優化之設計,我們提出了一個根據存取行為考量所設 計的位置投射機制來進一步利用平行的特性增加效能並且同時減少不必要的資料搬 移所帶來的效能下降。這個機制不只顯著地降低不適當的配置方法所帶來的效能損 耗,並且藉由減少額外寫入提升裝置壽命。最後,藉由一系列之實驗,我們驗證了 所提出方法之有效性,並得到了令人振奮的結果。 | zh_TW |
dc.description.abstract | Address mapping for flash storage devices has been a challenging design problem for controllers
because of the rapidly growing device capacity. On the other hand, the increasing number of chips bring about difficulties in design management of flash storage devices. In contrast to existing address mapping designs that focuses on improving caching mechanism efficiency, we propose a locality-based address remapping strategy to further utilize the parallelism to improve the performance and reduce unnecessary data write imposed by the improper data allocation. The experiments were conducted based on representative realistic workloads to evaluate the efficacy of the proposed scheme. The results reveal that the proposed management can not only improve the performance but also extend the endurance of the flash storage device. | en |
dc.description.provenance | Made available in DSpace on 2021-06-16T06:37:29Z (GMT). No. of bitstreams: 1 ntu-103-R01922129-1.pdf: 2157521 bytes, checksum: 61750ae67c40322477b1eb66ebf45b0b (MD5) Previous issue date: 2014 | en |
dc.description.tableofcontents | Acknowledgment ii
Abstract in Chinese iii Abstract iv Contents v List of Figures vii List of Tables viii 1 Introduction 1 2 System Architecture and Motivation 4 3 A Locality-based Address Remapping Strategy for NAND Flash Memory 8 3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 A Two-area-based Allocating Strategy . . . . . . . . . . . . . . . . . . . 10 3.2.1 Address Translation Managements . . . . . . . . . . . . . . . . . 10 3.2.2 The Handling of Read/Write Requests . . . . . . . . . . . . . . . 12 3.3 Switch Operation and Garbage Collection . . . . . . . . . . . . . . . . . 13 4 Performance Evaluation 18 4.1 Metrics and Experiment Setup . . . . . . . . . . . . . . . . . . . . . . . 18 4.2 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2.1 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2.2 Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5 Conclusion 22 Bibliography 24 Curriculum Vitae 26 | |
dc.language.iso | zh-TW | |
dc.title | 具存取行為考量之快閃記憶體位址再映射策略 | zh_TW |
dc.title | A Locality-based Address Remapping Strategy for NAND Flash
Memory | en |
dc.type | Thesis | |
dc.date.schoolyear | 102-2 | |
dc.description.degree | 碩士 | |
dc.contributor.coadvisor | 張原豪(Yuan-Hao Chang) | |
dc.contributor.oralexamcommittee | 逄愛君(Ai-Chun Pang),施吉昇(Chi-Sheng Shih),薛智文(Chih-Wen Hsueh),賴瑾(Jiin Lai) | |
dc.subject.keyword | 儲存系統,快閃記憶體,效能,存取行為,位址映射, | zh_TW |
dc.subject.keyword | storage system,flash memory,performance,locality,address mapping, | en |
dc.relation.page | 26 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2014-07-31 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 資訊工程學研究所 | zh_TW |
顯示於系所單位: | 資訊工程學系 |
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