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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/56430完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 吳瑞北 | |
| dc.contributor.author | Ming-Kai Kang | en |
| dc.contributor.author | 康明凱 | zh_TW |
| dc.date.accessioned | 2021-06-16T05:28:15Z | - |
| dc.date.available | 2014-08-17 | |
| dc.date.copyright | 2014-08-17 | |
| dc.date.issued | 2014 | |
| dc.date.submitted | 2014-08-14 | |
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Technol., vol. 1, no. 6, pp. 893–903, Jun. 2011. [44] 張長葆, “利用圓柱函數基底萃取直通矽晶穿孔柱陣列之電氣參數,” 國立臺灣大學碩士論文, 2013 | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/56430 | - |
| dc.description.abstract | 三維積體電路使用直通矽晶連通柱作為電氣連結，而訊號通過直通矽晶連通柱時，對其他直通矽晶連通柱和周遭的電路造成雜訊擾動，因此，減低雜訊擾動是一項重要的議題。
本論文提出使用金屬層用以降低直通矽晶連通柱對元件的耦合雜訊，對於不同的直通矽晶連通柱至元件的距離、不同的金屬層覆蓋比例以及不同的鄰近金屬層間距，觀察其耦合雜訊的變化。 耦合雜訊對於元件的基板電壓之擾動，造成元件的基板效應，從而對臨界電壓造成影響。本論文將耦合雜訊造成的元件基板電壓改變，求得因基板效應所造成之飽和區電流變動百分比。 最後提出設計曲線，可以確定飽和區電流變動百分比以及金屬層覆蓋比例，選擇適當的直通矽晶連通柱至元件的距離及鄰近金屬層間距。 | zh_TW |
| dc.description.provenance | Made available in DSpace on 2021-06-16T05:28:15Z (GMT). No. of bitstreams: 1 ntu-103-R01942001-1.pdf: 3575922 bytes, checksum: bcf60b46f9991f71ae86cbae5cc5c326 (MD5) Previous issue date: 2014 | en |
| dc.description.tableofcontents | 口試委員審定書 i
誌謝 iii 摘要 v Abstract vii 目錄 ix 圖目錄 xi 表目錄 xv 第1章 緒論 1 1.1 研究動機與簡介 1 1.2 文獻回顧與探討 5 1.3 研究貢獻 8 1.4 章節概述 9 第2章 基礎理論 11 2.1 多埠微波網路 [29] 11 2.2 直通矽晶連通柱對元件的耦合關係 15 2.3 金屬氧化物半導體場效電晶體之臨界電壓 22 2.4 金屬氧化物半導體場效電晶體之基板效應 25 第3章 金屬層與直通矽晶連通柱對元件的耦合係數之關係 27 3.1 無金屬層時直通矽晶連通柱對元件的耦合係數 27 3.2 金屬層線寬與直通矽晶連通柱對元件耦合係數之關係 33 3.3 金屬層間距與直通矽晶連通柱對元件耦合係數之關係 43 第4章 金屬層與直通矽晶連通柱對元件的基板效應之關係 53 4.1 訊號通過直通矽晶連通柱對元件基板效應之影響 53 4.2 金氧半場效電晶體的製程相關參數 55 4.3 訊號直通矽晶連通柱的金氧半電容效應 57 4.4 金屬層效應對臨界電壓的影響 65 4.5 金屬層效應對飽和區電流之影響 67 第5章 結論與未來展望 79 5.1 結論 79 5.2 未來展望 80 參考文獻 81 | |
| dc.language.iso | zh-TW | |
| dc.subject | 基板效應 | zh_TW |
| dc.subject | 三維積體電路 | zh_TW |
| dc.subject | 直通矽晶連通柱 | zh_TW |
| dc.subject | Through-silicon-via (TSV) | en |
| dc.subject | Body effect | en |
| dc.subject | Three-dimensional integrated circuit (3D-IC) | en |
| dc.title | 利用金屬層降低直通矽晶連通柱至元件耦合雜訊之設計 | zh_TW |
| dc.title | Design of Reducing TSV-to-Device Coupling Noise Using Metal Layers | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 102-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 劉致為,郭建男,洪子聖,林建民 | |
| dc.subject.keyword | 基板效應,三維積體電路,直通矽晶連通柱, | zh_TW |
| dc.subject.keyword | Body effect,Three-dimensional integrated circuit (3D-IC),Through-silicon-via (TSV), | en |
| dc.relation.page | 84 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2014-08-14 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電信工程學研究所 | zh_TW |
| 顯示於系所單位： | 電信工程學研究所 | |
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