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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 黃俊郎(Jiun-Lang Huang) | |
dc.contributor.author | Yu-Ru Lu | en |
dc.contributor.author | 盧昱儒 | zh_TW |
dc.date.accessioned | 2021-06-15T16:32:46Z | - |
dc.date.available | 2017-08-20 | |
dc.date.copyright | 2015-08-20 | |
dc.date.issued | 2015 | |
dc.date.submitted | 2015-08-13 | |
dc.identifier.citation | [1] J. P. Roth. 'Diagnosis of automata failures: A calculus and a method.' IBM journal of Research and Development vol. 10.4, July 1966, pp. 278-291.
[2] P. Goel. 'An implicit enumeration algorithm to generate tests for combinational logic circuits.' IEEE Transactions on Computers, vol. C-30.3, March 1981, pp. 215-222. [3] H. Fujiwara and T. Shimono. 'On the acceleration of test generation algorithms.' IEEE Transactions on Computers, vol. C-32.12, December 1993, pp. 1137-1144. [4] R. H. Klenke, R. D. Williams and J. H. Aylor. 'Parallel-processing techniques for automatic test pattern generation.' Computer, vol. 25.1, January 1992, pp. 71-84. [5] S. Patil and P. Banerjee. 'A parallel branch and bound algorithm for test generation.' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 9.3, March 1990, pp. 313-322. [6] S. Venkatraman, S. Seth and P. Agrawal. 'Parallel test generation with low communication overhead.' In VLSI Design, January 1995, pp. 116-120. [7] X. Cai, P. Wohl J. A. Waicukauski and P. Notiyath. 'Highly efficient parallel ATPG based on shared memory.' In International Test Conference, November 2010, pp. 1-7. [8] X. Cai, P. Wohl and D. Martin. 'Fault sharing in a copy-on-write based ATPG system.' In International Test Conference, October 2014, pp. 1-8. [9] R. Butler, B. Keller, R. Paliwalm, R. Schoonover and J. Swenton. 'Design and implementation of a parallel automatic test pattern generation algorithm with low test vector count.' In International Test Conference, October 2000, pp. 530-537. [10] S. J. Chandra and J. H. Patel. 'Test generation in a parallel processing environment.' In International Conference on Computer Design, October 1988, pp.11-14. [11] S. Parkes, P. Banerjee and J Patel. 'ProperHITEC: A portable, parallel, object-oriented approach to sequential test generation.' In Design Automation conference, June 1994, pp. 717-721. [12] C. Gil and J. Ortega. 'Parallel Test Generation using circuit partitioning and spectral techniques.' In International Parallel and Distributed Processing Symposium, January 1998, pp. 264-270. [13] J. C. Y. Ku, R. H. –M. Huang, L. Y. –Z. Lin and C. H. –P. Wen. 'Suppressing test inflation in shared-memory parallel Automatic Test Pattern Generation.' In Design Automation Conference, January 2014, pp. 664-669 [14] R. H. Klenke, R. D. Williams and J. H. Aylor. 'Parallelization methods for circuit partitioning based parallel automatic test pattern generation.' In VLSI Test Symposium, April 1993, pp. 71-78. [15] X. Cai and P. Wohl. 'A distributed-multicore hybrid ATPG system.' In International Test Conference, September 2013, pp. 1-7. [16] S. J. Chandra and J. H. Patel. 'Test generation in a parallel processing environment.' In International Conference on Computer Design, October 1988, pp.11-14. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/52894 | - |
dc.description.abstract | 為了解決自動化測試圖樣產生技術 (Automatic Test Pattern Generation) 的消耗時間,許多加速自動化測試圖樣產生技術的平行化技術被發表。但是大部分的平行化技術有測試圖樣 (Test Pattern) 膨脹的缺陷。
在這本論文中,為了可以降低測試資料量,我們提出了一個可以改善動態壓縮效能 (Dynamic Compaction) 的技術。這個技術使用了平行化搜尋空間分割 (Parallel Search Space Partitioning) ,而這個技術被實作在一個多執行序系統 (Multi-threading System) 上,其執行序使用共享儲存記憶體 (Shared Memory)的方式交換資料 。同時,為了減少執行的時間,我們提出的搜尋空間分割技術是在一個負載平衡 (Load Balancing) 之下實做出來的。 這個技術在ITC99的測試電路與兩個工業電路上驗證結果,而這些電路的實驗結果表示我們所提出的技術可以達成降低測試圖樣這個目標,且最多高達18%。 | zh_TW |
dc.description.abstract | Many parallel Automatic Test Pattern Generation (ATPG) techniques have been proposed to speed up the time-consuming test generation process. However, most of the parallel ATPG’s suffer test pattern inflation.
This thesis proposes a dynamic compaction aware search space partitioning parallel ATPG that is based on a shared memory multi-threading system. The proposed ATPG can improve the dynamic compaction efficiency to reduce the test pattern count. Our technique implementation is also based on dynamic load balancing. Our technique is validated by ITC99 benchmark circuits and two industry designs. Experimental results show that the proposed TPG can reduce the test pattern count by up to 18%. | en |
dc.description.provenance | Made available in DSpace on 2021-06-15T16:32:46Z (GMT). No. of bitstreams: 1 ntu-104-R02943158-1.pdf: 1654312 bytes, checksum: 0c072db1aa3474f95d7985084f3590c2 (MD5) Previous issue date: 2015 | en |
dc.description.tableofcontents | 口試委員會審定書 #
誌謝 i 中文摘要 ii ABSTRACT iii CONTENTS iv LIST OF FIGURES vi LIST OF TABLES viii Chapter 1 Introduction 1 Chapter 2 Preliminaries 3 2.1 Typical Serial ATPG 3 2.2 Parallel Processing 4 2.3 Prior Works of Parallel ATPG 5 2.3.1 Fault Partitioning 5 2.3.2 Search Space Partitioning 7 2.3.3 Heuristic parallelization 10 2.3.4 Circuit Partitioning 10 Chapter 3 Proposed Technique 12 3.1 Motivation 12 3.2 System Architecture 12 3.2.1 Parallel Architecture 12 3.2.2 Shared memory 13 3.3 Test Pattern Generation Algorithm 14 3.3.1 The Master Process 15 3.3.2 The Slave Process 16 3.4 Search Space Partitioning 18 3.4.1 Dynamic Load Balancing 18 3.4.2 Partitioning method 20 3.4.3 The Minimized Specified Bits Current Pattern 21 3.4.4 Search Space Constraint 21 3.5 Backtrack Limit Experiments 24 3.5.1 Backtrack Limit Issue 24 3.5.2 Unnecessary divided search space 24 Chapter 4 Experiment 29 4.1 Experiment Setup 29 4.2 Proposed Parallel ATPG versus Serial ATPG 30 4.2.1 Normalization Pattern Count Reduction 30 4.2.2 Test Coverage 32 4.2.3 Total and Average Assigned Bits 33 4.2.4 Execution Time Reduction 34 4.3 Fast and best solution comparison 37 4.4 Fault Analysis 38 4.4.1 HTD Faults and ETD Faults Ratio 38 4.5 Summary 41 Chapter 5 Conclusions 42 REFERENCE 43 | |
dc.language.iso | en | |
dc.title | 利用搜索空間分割技術改善動態壓縮效能之平行化自動測試圖樣產生技術 | zh_TW |
dc.title | Improving Dynamic Compaction Efficiency by Search Space Partitioning Based Parallel ATPG | en |
dc.type | Thesis | |
dc.date.schoolyear | 103-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 呂學坤(Shyue-Kung Lu),溫宏斌(Hung-Pin Wen) | |
dc.subject.keyword | 自動化測試圖樣產生技術,動態壓縮,平行化,減少測試圖樣,搜索空間分割, | zh_TW |
dc.subject.keyword | ATPG,Dynamic compaction,Parallel,test pattern reduction,Search space partitioning, | en |
dc.relation.page | 0 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2015-08-13 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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ntu-104-1.pdf 目前未授權公開取用 | 1.62 MB | Adobe PDF |
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