請用此 Handle URI 來引用此文件:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/5080
標題: | 伺服器非揮發記憶體之跨層級設計與最佳化 Cross-Layer Design and Optimization for Non-Volatile Memory in Servers |
作者: | Ren-Shuo Liu 呂仁碩 |
指導教授: | 楊佳玲(Chia-Lin Yang) |
關鍵字: | 快閃記憶體,相變式記憶體,儲存系統,儲存快取,主記憶體, NAND flash memory,phase change memory,primary storage,storage cache,main memory, |
出版年 : | 2014 |
學位: | 博士 |
摘要: | 雲端運算、社群網路、巨量資料分析等前瞻應用快速發展,低功率且高效能的伺服器是這類應用最重要的根基之一。然而傳統伺服器架構受動態記憶體(dynamic RAM, DRAM)與硬式磁碟(hard disk drive, HDD)的先天缺點限制,已逐漸難以符合此類需求。動態記憶體以半導體電容作為儲存單元,無法避免漏電且難以微縮製程。硬式磁碟必須使用磁頭與馬達等機械元件,要降低功耗與增進效能非常困難。此外,動態記憶體與硬式磁碟兩者的存取速度相差逾萬倍、存取方法大相逕庭,也是伺服器提高效能及降低功率的一大阻礙。
欲解決上述問題,引進非揮發記憶體(non-volatile memory)技術來設計伺服器是目前最有前景的方案之一,尤以快閃記憶體(NAND flash memory) 及相變式記憶體(phase-change memory, PCM)最成熟且最受矚目。相較於硬式磁碟,快閃記憶體與相變式記憶體不需機械元件,因此反應速度較快、功耗較低、且發熱較少;相較於動態記憶體,快閃記憶體與相變式記憶體的密度較高且具有非揮發性。因此,快閃記憶體適合用於伺服器中,作為硬式磁碟的快取,甚或取代硬式磁碟。相變式記憶體適合大量取代伺服器中的動態記憶體,作為主記憶體。 本論文中,我針對使用快閃記憶體與相變式記憶體之伺服器,提出新的觀點並創新跨層級設計與最佳化。有別於過去許多快閃記憶體研究著重檔案系統與快閃記憶體轉換層(flash translation layer, FTL)等純軟體層級設計,我的研究特別關注快閃記憶體元件層級日漸顯著的非理想性質、並同時設計軟硬體階層加以處理。此外,有別於過去大多數相變式記憶體研究將相變式記憶體視為單純的工作記憶體或單純的儲存媒體,我的研究著重將相變式記憶體同時作為兩種用途,並重新檢視作業系統、記憶體控制器、以及記憶體元件層級相關設計。 本論文提出三種創新架構設計:Retention Relaxation、DuraCache、以及NVM Duet。Retention Relaxation允許伺服器在執行時期可選擇以較低的維持性(retention)將資料寫入快閃記憶體,藉以最佳化儲存系統的效能。DuraCache 重新檢視當快閃記憶體作為儲存系統的快取而非主要儲存媒體本身時,可以放寬那些設計限制,藉以延長快閃記憶體的壽命。NVM Duet允許作業系統層將資料的用途(工作記憶體或儲存媒體)傳遞到記憶體控制器及記憶體元件,以增進記憶體系統的效能。 本論文之成果顯著地增進現有伺服器中非揮發記憶體之設計與管理技術。上述三種架構已藉由建模(modeling)、量測(characterization)、以及模擬(simulation)分析驗證功效。更重要的,本論文開啟了非揮發記憶體設計與最佳化的新方向:已有許多後續發表的研究採用並延伸本論文所提之架構與概念,相關的概念未來將受到更多的關注。 Low-power, high-performance servers are crucial to emerging applications such as cloud computing, social networking, and big data analytics. However, conventional server architectures are challenging in fulfilling this need due to the inherent shortcomings of dynamic RAM (DRAM) and hard disk drives (HDDs). DRAM is made of semiconductor capacitors, which are leaky and difficult to shrink. HDDs consist of mechanical parts such as moving arms and spinning platters, which restrict achievable performance and consume noticeable power. Moreover, the sharp distinctions between DRAM and HDDs in terms of access latencies (0.1 us vs. 1 ms) and access methods (CPU load/stores vs. OS-involved block I/Os) also complicate software design and hinder achieving low power and high performance. A promising trend to address the abovementioned challenges is to adopt non-volatile memory (NVM) in servers. NAND flash memory (flash for short) and phase-change memory (PCM) are among the most mature and appealing technologies. Compared with HDDs, flash and PCM exhibit better responsiveness, consume lower power, and dissipate less heat because of the absence of mechanical moving parts; compared with DRAM, PCM and flash exhibit advantages in terms of density and non-volatility. Flash is suitable for serving as the caches of HDDs or even replacing the majority of HDDs. PCM is suitable for replacing the majority of DRAM and serving as the main memory. In this dissertation, I identify new insights and innovate cross-layer design and optimization for adopting flash and PCM in servers. A large body of prior flash studies focus on software layers including file systems and flash translation layers (FTLs), whereas I focus on collaborating hardware and software layers considering the increasingly critical nonidealness of flash devices. In addition, most prior PCM studies focus on architecting PCM as either pure working memory or pure storage, whereas I focus on revisiting and redesigning hardware and software layers so that PCM can efficiently and simultaneously serve as both roles. Specifically, this dissertation presents three innovative architectures, Retention Relaxation, DuraCache, and NVM Duet, to best adopt flash and PCM in servers. Retention Relaxation allows data to be written into flash-based storage with runtime-reduced retention levels to optimize the performance of flash-based storage. DuraCache revisits and exploits what design constraints can be relaxed for flash that serves as storage caches (instead of primary storage) to prolong the lifetime of flash-based storage caches. NVM Duet allows operating systems to inform memory controllers and memory devices of the usage cases of data (working memory or storage) to optimize the performance of PCM-based main memory. This dissertation makes a significant step toward taking true advantage of NVM in servers. Evaluation results based on modeling, characterization, and simulation demonstrate that the above proposed architectures are effective. More importantly, this dissertation opens up new space for NVM design and optimization. There has been a trend of more and more studies adopting and extending the proposed architectures and concepts, and I anticipate these concepts to keep receiving increasing attention in the future. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/5080 |
全文授權: | 同意授權(全球公開) |
顯示於系所單位: | 資訊工程學系 |
文件中的檔案:
檔案 | 大小 | 格式 | |
---|---|---|---|
ntu-103-1.pdf | 11.13 MB | Adobe PDF | 檢視/開啟 |
系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。