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標題: | 氮化鋁鎵/氮化鎵異質接面鳍式高電子遷移率電晶體及大面積高電流功率電晶體的製作與開發 Fabrication and Development of AlGaN/GaN Heterojunction Fin Structure High Electron Mobility Transistors and Large Area High Current PowerTransistors |
作者: | Min Yang 楊旻 |
指導教授: | 吳肇欣(Chao-Hsin Wu) |
關鍵字: | 鰭式場效電晶體,高載子遷移率電晶體,短通道效應,臨界電壓,增強式, FinFET,HEMT,short channel effects,threshold voltage,enhancement mode, |
出版年 : | 2016 |
學位: | 碩士 |
摘要: | 本篇論文旨在開發出增強式操作的元件,我們沒有採用一般氟離子電漿處理閘極下方區域或是磊晶一層p型氮化鎵或是p型氮化鋁鎵覆蓋層於材料表面,我們採用鳍式結構,希望能夠藉由鳍式結構帶來較好的通道控制力,使臨界電壓能往正方向移動來達到增強式操作。在本篇論文第一章我們簡單的介紹研究動機,氮化鎵材料基本特性,及其異質接面應用在高電子遷移率電晶體的基本原理與論文實驗架構。第二章我們研究了鰭式結構對氮化鋁鎵�氮化鎵高電子遷移率電晶體的臨界電壓,導通/關閉狀態電流密度的影響,發現將鰭通道寬度由6微米縮小至2微米時,臨界從-3.62V平移至-2.9V與汲極引致能障下降從52.16mV/V平移至21mV/V,短通道效應獲得改善。由第二章的實驗結果,在第三章中我們分別利用原子層沉積與電子束微影的技術製作了鰭式金氧半與奈米鰭式高電子遷移率電晶體。希望能夠結合鳍式結構帶來的較佳控制能力與增加閘極操作電壓得到高電流增強式元件,也比較微米與奈米尺寸鰭寬的電晶體,將鰭狀通道寬度縮小到200奈米以下,可以觀察到臨界電壓(subthreshold voltage)從-3.33伏特平移到-0.48伏特,雖然還未達到臨界電壓大於0V,但其臨界電壓的平移量已遠超過一般從平面式電晶體微縮到2微米鳍寬的電晶體。在第四章中,我們將前面兩章的製程應用在大面積高電流的功率元件上。為了達到大電流操作,我們採用平面式結構,利用閘極掘入與沉積氧化層期望來做出增強式高電流大面積元件,並討論大元件關閉狀態特性較差,閘極無法控制通道的原因,並在第五章做出論文的結論。 In this thesis, we focus on developing enhancement-mode operation devices. Instead of using conventional fluorine plasma treatment underneath the gate or growing p-type GaN or p-type AlGaN over the AlGaN barrier, we use fin structures, hoping to make threshold voltages shift to positive values by better controllability of fin structures. In chapter one, we simply introduce the motivation of our research, basic properties of GaN, operation of High Electron Mobility Transistor (HEMT), and experimental setup. In chapter two, we investigate the effect of fin structures on threshold voltages and on/off current density. We observe that by shrinking the fin width from 6μm to 2μm, threshold voltage and DIBL shift from -3.62V to -2.9V and 52.16mV/V to 21mV/V, respectively. Short channel effects are improved by fin structures. From the result of chapter two, we fabricate MOSFinHEMT and nano-scale FinHEMT by adopting atomic layer deposition and e-beam lithography, hoping to fabricate high current enhancement-mode device by combining the advantages brought from fin structures and increased applied gate voltages. By shrinking the fin width below 200nm, threshold voltage shifts from -3.33V to -0.48V. Although threshold voltage still is less than 0V, the threshold voltage shift is larger than that from planar device to 2μm-fin-width device. In chapter four, we applied the fabrication process of last two chapter on large area high current power devices. In order to obtain high current operation, we adopt planar structure and discuss the reasons behind poor off-state performance and poor controllability of large area devices. In chapter five, we summarize and make conclusions of our thesis. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/49227 |
DOI: | 10.6342/NTU201602886 |
全文授權: | 有償授權 |
顯示於系所單位: | 電子工程學研究所 |
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