應用於毫米波無線通訊系統之相位鍵移調變/解調電路及頻率合成器

Abstract

在本論文中，將會介紹四個應用於毫米波無線通訊的電路系統。包括一個5-Gb/s資料傳輸率、5-GHz載波頻率的差分相干二位元相位鍵移調變/解調器，一個40-GHz頻率合成器，以及兩個操作於W-band (75 GHz~110 GHz)的二位元以及四位元相位鍵移調變收發機。 5-Gb/s資料傳輸率、5-GHz載波頻率的差分相干二位元相位鍵移調變/解調器以90-nm CMOS製程實現。其中包括了一個差分相干編碼器，二位元相位鍵移調變器，以及利用延遲器所實現的解調器。這個晶片在2^(31)-1 PRBS的編碼下，可達到位元誤碼率小於10^ (-12)。在電路1.2伏特的操作電壓下，消耗35毫瓦，晶片面積為0.29平方公釐。 40-GHz頻率合成器以65-nm CMOS製程製造，將應用於60-GH無線通訊系統中，提供20-GHz的正交中頻信號以及40-GHz的本地震盪器信號。為了符合IEEE 802.15.3c的標準，須提供寬頻(38.88 GHz~43.20 GHz)震盪輸出，因此採用八段式頻率震盪器，並包括可適性切段數位電路區塊。本頻率合成器的輸出頻率範圍達到4.58 GHz，在1-MHz偏移頻率下90.0 dBc/Hz 的相位雜訊。在1.2伏特(頻率震盪器1.6伏特)的操作電壓下，消耗功率為92毫瓦，晶片面積為0.44平方公釐。 操作於W-band的二位元以及四位元相位鍵移調變收發機以65-nm CMOS製程實現。本系統使用Costas loop達成載波復原與解調，二位元相位鍵移調變收發機傳輸4.5 Gb/s的資料速率位元誤碼率小於10^(-9)，消耗功率327毫瓦，晶片面積1.28平方公釐。四位元相位鍵移調變收發機傳輸3.5 Gb/s的資料速率位元誤碼率小於10^(-11)，消耗功率378毫瓦，晶片面積1.4平方公釐。

In this thesis, four circuit systems which can be applied to mm-wave wireless communication are demonstrated. It includes a 5-Gb/s data rate and 5-GHz carrier rate differential binary phase-shift keying (DBPSK) modulator/demodulator set, a 40-GHz frequency synthesizer, and two W-band wireless transceivers. One of the transceivers utilizes binary phase-shift keying (BPSK) modulation and its carrier frequency is 84 GHz and the other extends to quadrature phase-shift keying (QPSK) modulation at 87 GHz. The 5-Gb/s data rate and 5-GHz carrier rate DBPSK modulator/demodulator set is implemented in 90-nm CMOS technology. It consists of a differential encoder, a BPSK modulator, and a demodulator which is realized with automatic delay-locked unit. It achieves bit error rate (BER) < 10^(-12) for 2^(31)-1 PRBS, and consumes 35 mW from 1.2-V supply. The chip area is 0.29 mm2. The 40-GHz frequency synthesizer is fabricated in 65-nm CMOS technology, providing the 20-GHz I/Q signals and 40-GHz local oscillator (LO) clock for 60-GHz wireless application. To coincide with the IEEE 802.15.3c standard, this frequency synthesizer is required to offer a wideband output (38.88 GHz ~ 43.20 GHz), so an 8-band voltage-controlled oscillator (VCO) with adaptive digital-controlled unit is applied. It achieves a locking range of 4.58 GHz, and the phase noise is 90.0 dBc/Hz at 1-MHz offset. The power consumption is 92 mW from 1.2-V supply (VCO from 1.6-V), and the chip area is 0.44 mm2. Finally, two fully-integrated BPSK and QPSK transceivers operating at W-band [carrier frequency = 84 GHz (BPSK), and 87 GHz (QPSK)] are presented. Including RF front-end, Costas-loop-based carrier and data recovery, and antenna assembly technique. The BPSK transceiver prototype achieves 4.5-Gb/s data link with BER < 10^(−9) while consuming 202 mW (Tx) and 125 mW (Rx) from a 1.2-V supply. For QPSK TRx, on the other hand, it achieves 3.5-Gb/s data link with BER < 10^(−11) while consuming 212 mW (Tx) and 166 mW (Rx) from a 1.2-V supply.