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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/48044完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李致毅(Jri Lee) | |
| dc.contributor.author | Yu-Ching Yeh | en |
| dc.contributor.author | 葉又菁 | zh_TW |
| dc.date.accessioned | 2021-06-15T06:45:02Z | - |
| dc.date.available | 2016-07-07 | |
| dc.date.copyright | 2011-07-07 | |
| dc.date.issued | 2011 | |
| dc.date.submitted | 2011-06-28 | |
| dc.identifier.citation | [1] IEEE 802.15.3c. [Online]. Available: https://mentor.ieee.org/802.15/file/07
/15-07-0760-03-003c-tensorcom-phy-presentation.ppt [2] H. Krishnaswamy et al., “A fully integrated 24 GHz 4-channel phased-array transceiver in 0.13um CMOS based on a variable-phase ring oscillator and PLL architecture,” IEEE Int. Solid-State Circuits Conf.(ISSCC) Dig. Tech. Papers, pp. 124-125, Feb. 2007. [3] A. Babakhani et al., “A 77-GHz phased-array transceiver with on-chip antennas in silicon: Receiver and antennas,” IEEE J. Solid-State Circuits, vol. 41, pp. 2795–2805, Dec. 2006. [4] Sibeam. [Online]. Available: http://www.sibeam.com [5] J. Lee et al., “A Low-Power Low-Cost Fully-Integrated 60-GHz Transceiver System With OOK Modulation and On-Board Antenna Assembly,” IEEE J. Solid-State Circuits, vol. 45, pp. 264-275, Feb. 2010. [6] A. Oncu et al., “1Gbps/ch 60GHz CMOS multichannel millimeter-wave repeater,” Symp. VLSI Circuits Dig. Tech. Papers, pp. 93-94, June 2010. [7] H. Wang et al., “A 60-GHz FSK Transceiver with Automatically-Calibrated Demodulator in 90-nm CMOS,” Symp. VLSI Circuits Dig. Tech. Papers, pp. 95-96, June 2010. [8] C. Marcu et al., “A 90nm CMOS Low-Power 60 GHz Transceiver with Integrated Baseband Circuitry,” IEEE J. Solid-State Circuits, vol. 44, Dec. 2009. [9] A. Tomkins et al., “A Zero-IF 60 GHz 65 nm CMOS Transceiver With Direct BPSK Modulation Demonstrating up to 6 Gb/s Data Rates Over a 2 m Wireless Link,” IEEE J. Solid-State Circuits, vol. 44, pp. 2085-2099, Aug. 2009. [10] J. Lee et al., “Design and Comparison of Three 20-Gb/s Backplane Transceivers for Duobinary, PAM4, and NRZ Data,” IEEE J. Solid-State Circuits, vol. 43, pp. 2120-2133, Sep. 2008. [11] H. Chang et al., “A 0.7-2-GHz self-calibrated multiphase delay-locked loop,” IEEE J. Solid-State Circuits, vol. 41, pp. 1051-1061, May 2006. [12] A. Kral et al., “RF-CMOS oscillators with switched tuning,” IEEE Custom Integrated Circuits Conference, pp.555-558, May 1998. [13] A. Samuel et al., “A multi-band single-loop PLL frequency synthesizer with dynamically-controlled switched tuning VCO, ” IEEE Circuits and Systems, vol.2, pp.818-821 , Aug. 2000. [14] J. Lee et al., “A 20-Gb/s Full-Rate Linear Clock and Data Recovery Circuit With Automatic Frequency Acquisition,” IEEE J. Solid-State Circuits, vol. 44, pp. 3590-3602, Dec. 2009. [15] J. Lee et al., “A 75-GHz Phase-Locked Loop in 90-nm CMOS Technique,” IEEE J. Solid-State Circuits, vol. 43, pp. 1414-1426, June 2008. [16] C. Vaucher et al., “A Wide-Band Tuning System for Fully Integrated Satellite Receivers,” IEEE J. Solid-State Circuits, vol. 33, no. 7, pp. 987-998, July 1998. [17] O. Richard et al., “A 17.5-to-20.94GHz and 35-to-41.88GHz PLL in 65nm CMOS for wireless HD applications,” IEEE Int. Solid-State Circuits Conf.(ISSCC) Dig. Tech. Papers, pp. 252-253, Feb. 2010. [18] M. Hammad et al., “A 40-GHz phase-locked loop for 60-GHz sliding-IF transceivers in 65nm CMOS,” IEEE Asian Solid-State Circuits Conf., 2010, pp. 1-4. [19] D. Murphy, et al., “A Low Phase Noise, Wideband and Compact CMOS PLL for Use in a Heterodyne 802.15.3c Transceiver,” IEEE J. Solid-State Circuits, vol. 46, pp. 1-12, July 2011. [20] “Allocations and Service Rules for the 71-76 GHz, 81-86 GHz, and 92-95 GHz Bands,” FCC Notice of Proposed Rule Making 02-180., June 2002. [21] F. Lin et al., “A Low Power 60GHz OOK Transceiver System in 90nm CMOS with Innovative On-Chip AMC Antenna,” IEEE Asian Solid-State Circuits Conf., 2009, pp. 349-354. [22] J. Wells, “Multigigabit Wireless Connectivity at 70, 80 and 90 GHz,” RF Design Magazine, May 2006. [23] C. A. Balanis, Antenna Theory Analysis and Design, 3rd ed. New York: Wiley, 2005. [24] J. P. Coastas et al., “Synchronous Communications,” Proceedings of the IRE, vol. 44, pp. 1713-1718, Dec. 1956. [25] C. Chien et al., “A Single-Chip 12.7 Mchips/s Digital IF BPSK Direct Sequence Spread-Spectrum Transceiver in 1.2 µm CMOS,” IEEE J. Solid-State Circuits, vol. 29, no. 12, pp. 1614-1623, Dec. 1994. [26] B. Gilbert, “A Precise Four-Quadrant Multiplier with Subnanosecond Response,” IEEE J. Solid-State Circuits, vol. SC-3, pp. 365-373, Dec. 1968. [27] B. Razavi et al., “A 13.4-GHz CMOS Frquency Divider,” IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 224-225, Feb. 1994. [28] J. Yuan et al., “High-Speed CMOS Circuit Technique,” IEEE J. Solid-State Circuits, vol. 24, pp. 62-70, Feb. 1989. [29] I. Sarkas et al., “An 18-Gb/s, Direct QPSK Modulation, SiGe BiCMOS Transceiver for Last Mile Links in the 70-80 GHz Band,” IEEE J. Solid-State Circuits, vol. 45, pp. 1968-1980, Oct. 2010. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/48044 | - |
| dc.description.abstract | 在本論文中，將會介紹四個應用於毫米波無線通訊的電路系統。包括一個5-Gb/s資料傳輸率、5-GHz載波頻率的差分相干二位元相位鍵移調變/解調器，一個40-GHz頻率合成器，以及兩個操作於W-band (75 GHz~110 GHz)的二位元以及四位元相位鍵移調變收發機。
5-Gb/s資料傳輸率、5-GHz載波頻率的差分相干二位元相位鍵移調變/解調器以90-nm CMOS製程實現。其中包括了一個差分相干編碼器，二位元相位鍵移調變器，以及利用延遲器所實現的解調器。這個晶片在2^(31)-1 PRBS的編碼下，可達到位元誤碼率小於10^ (-12)。在電路1.2伏特的操作電壓下，消耗35毫瓦，晶片面積為0.29平方公釐。 40-GHz頻率合成器以65-nm CMOS製程製造，將應用於60-GH無線通訊系統中，提供20-GHz的正交中頻信號以及40-GHz的本地震盪器信號。為了符合IEEE 802.15.3c的標準，須提供寬頻(38.88 GHz~43.20 GHz)震盪輸出，因此採用八段式頻率震盪器，並包括可適性切段數位電路區塊。本頻率合成器的輸出頻率範圍達到4.58 GHz，在1-MHz偏移頻率下90.0 dBc/Hz 的相位雜訊。在1.2伏特(頻率震盪器1.6伏特)的操作電壓下，消耗功率為92毫瓦，晶片面積為0.44平方公釐。 操作於W-band的二位元以及四位元相位鍵移調變收發機以65-nm CMOS製程實現。本系統使用Costas loop達成載波復原與解調，二位元相位鍵移調變收發機傳輸4.5 Gb/s的資料速率位元誤碼率小於10^(-9)，消耗功率327毫瓦，晶片面積1.28平方公釐。四位元相位鍵移調變收發機傳輸3.5 Gb/s的資料速率位元誤碼率小於10^(-11)，消耗功率378毫瓦，晶片面積1.4平方公釐。 | zh_TW |
| dc.description.abstract | In this thesis, four circuit systems which can be applied to mm-wave wireless communication are demonstrated. It includes a 5-Gb/s data rate and 5-GHz carrier rate differential binary phase-shift keying (DBPSK) modulator/demodulator set, a 40-GHz frequency synthesizer, and two W-band wireless transceivers. One of the transceivers utilizes binary phase-shift keying (BPSK) modulation and its carrier frequency is 84 GHz and the other extends to quadrature phase-shift keying (QPSK) modulation at 87 GHz.
The 5-Gb/s data rate and 5-GHz carrier rate DBPSK modulator/demodulator set is implemented in 90-nm CMOS technology. It consists of a differential encoder, a BPSK modulator, and a demodulator which is realized with automatic delay-locked unit. It achieves bit error rate (BER) < 10^(-12) for 2^(31)-1 PRBS, and consumes 35 mW from 1.2-V supply. The chip area is 0.29 mm2. The 40-GHz frequency synthesizer is fabricated in 65-nm CMOS technology, providing the 20-GHz I/Q signals and 40-GHz local oscillator (LO) clock for 60-GHz wireless application. To coincide with the IEEE 802.15.3c standard, this frequency synthesizer is required to offer a wideband output (38.88 GHz ~ 43.20 GHz), so an 8-band voltage-controlled oscillator (VCO) with adaptive digital-controlled unit is applied. It achieves a locking range of 4.58 GHz, and the phase noise is 90.0 dBc/Hz at 1-MHz offset. The power consumption is 92 mW from 1.2-V supply (VCO from 1.6-V), and the chip area is 0.44 mm2. Finally, two fully-integrated BPSK and QPSK transceivers operating at W-band [carrier frequency = 84 GHz (BPSK), and 87 GHz (QPSK)] are presented. Including RF front-end, Costas-loop-based carrier and data recovery, and antenna assembly technique. The BPSK transceiver prototype achieves 4.5-Gb/s data link with BER < 10^(−9) while consuming 202 mW (Tx) and 125 mW (Rx) from a 1.2-V supply. For QPSK TRx, on the other hand, it achieves 3.5-Gb/s data link with BER < 10^(−11) while consuming 212 mW (Tx) and 166 mW (Rx) from a 1.2-V supply. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T06:45:02Z (GMT). No. of bitstreams: 1 ntu-100-R97943172-1.pdf: 4332662 bytes, checksum: ab4ab82a9772e66588eadbc4fce609ef (MD5) Previous issue date: 2011 | en |
| dc.description.tableofcontents | 摘要 i
ABSTRACT ii CONTENTS iv LIST OF FIGURES vii LIST OF TABLES x Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 4 Chapter 2 A 5 Gb/s Data Rate, 5-GHz Carrier Rate DBPSK Modulator/Demodulator Set in 90-nm CMOS 5 2.1 Introduction 5 2.2 System Architecture 6 2.2.1 Modulator 6 2.2.2 Demodulator 7 2.3 Building Blocks 8 2.3.1 Differential Encoder 9 2.3.2 Phase Selector 10 2.3.3 Delay Chain 10 2.3.4 Phase Detector 12 2.3.5 Band Controller 13 2.4 Measurement Results 15 2.5 Summary 18 Chapter 3 A 40-GHz Phase-Locked Loop for Use in a Heterodyne 802.15.3c Transceiver in 65-nm CMOS 20 3.1 Introduction 20 3.2 System Design Considerations 22 3.3 Building Blocks 23 3.3.1 40-GHz VCO and Buffers 23 3.3.2 Divider Chain 25 3.4 Measurement Results 26 3.5 Summary 31 Chapter 4 W-band BPSK/QPSK transceivers with Costas-Loop Carrier Recovery in 65-nm CMOS 32 4.1 Introduction 32 4.2 Carrier Recovery and Demodulation 35 4.2.1 BPSK 35 4.2.2 QPSK 38 4.3 Transmitter Architecture 40 4.3.1 BPSK 40 4.3.2 QPSK 41 4.4 Building Blocks 42 4.4.1 VCO and First Divider 42 4.4.2 BPSK modulator 43 4.4.3 QPSK modulator 44 4.5 Measurement Results 45 4.5.1 BPSK 46 4.5.2 QPSK 48 4.6 Summary 50 Chapter 5 Conclusions 52 Bibliography 54 | |
| dc.language.iso | en | |
| dc.subject | W-band | zh_TW |
| dc.subject | 相位鍵移調變 | zh_TW |
| dc.subject | 毫米波無線通訊 | zh_TW |
| dc.subject | 頻率合成器 | zh_TW |
| dc.subject | 60-GHz | zh_TW |
| dc.subject | Binary phase-shift keying (BPSK) | en |
| dc.subject | frequency synthesizer | en |
| dc.subject | mm-wave wireless communication | en |
| dc.subject | quadrature phase-shift keying (QPSK) | en |
| dc.subject | W-band | en |
| dc.subject | 60-GHz | en |
| dc.title | 應用於毫米波無線通訊系統之相位鍵移調變/解調電路及頻率合成器 | zh_TW |
| dc.title | PSK Modulation/Demodulation Circuits and Frequency Synthesizer for mm-Wave Wireless Communication | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 99-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 盧奕璋,盧信嘉 | |
| dc.subject.keyword | 相位鍵移調變,毫米波無線通訊,頻率合成器,60-GHz,W-band, | zh_TW |
| dc.subject.keyword | Binary phase-shift keying (BPSK),quadrature phase-shift keying (QPSK),mm-wave wireless communication,frequency synthesizer,60-GHz,W-band, | en |
| dc.relation.page | 56 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2011-06-28 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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