以偏移式鎖相迴路為基礎應用於SATA III之展頻時脈產生器

Abstract

在現今可攜式行動裝置被廣泛應用之下，為了達到高速的資料傳輸速度，個人電腦與外部儲存元件之間的高速介面變的更為重要。當資料在高速傳遞時，系統將遭受由高頻時脈所產生的電磁干擾。這種存在於電子產品中的非理想效應會造成嚴重的問題而必須被處理。SATA一種最具未來性的技術之ㄧ，並可提供高達6Gp/s的大頻寬。在SATA規範中，藉由展頻時脈技術來分散主要載波能量以達到降低電磁干擾的目的。 此論文提出一個以偏移式鎖相迴路為基礎，應用於SATA III的展頻時脈產生器。在此架構中，利用直接數位頻率合成器產生一個低頻的展頻時脈，並將此訊號藉由單邊帶混頻器升頻以產生一個高頻的參考調變輸入訊號。當達到鎖定狀態時，偏移式鎖相迴路將會產生所需的展頻時脈輸出。所設計的展頻時脈產生器製作使用標準0.11-μm互補金氧半導體邏輯製程且晶片面積為1.071 x 0.945 mm2，在1伏特電壓源供應下，功率消耗為15.22 mW。

As portable devices are widely used nowadays, the high-speed interfaces between the personal computer and the external storage devices are becoming critical in order to achieve high data transmission rate. When operating at high data rate, the systems often suffer from the electromagnetic interference (EMI) which is caused by the high-frequency clock. This non-ideal effect in electronic products is a serious issue which must be dealt with. Serial AT Attachment (SATA) is one of the most promising technologies providing large bandwidth up to 6 Gb/s. SATA specification defines an EMI reduction method using spread-spectrum clocking (SSC) to reduce the peak EMI emission by spreading the carrier frequency. A spread spectrum clock generator (SSCG) based on an offset phase-locked loop (OPLL) for the Serial AT Attachment 3 (SATA III) is presented in this thesis. In the proposed architecture, a low-frequency spread spectrum signal is synthesized by a direct digital frequency synthesizer (DDFS) and mixed with a high frequency signal to produce a higher modulated reference source. The OPLL is employed to lock its output with the modulated reference to generate the desired spread spectrum clock. This SSCG is fabricated in a 0.11-μm CMOS technology and its area is 1.071 x 0.945 mm2. It draws 15.22 mW from a 1 V supply.