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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/46869完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李泰成 | |
| dc.contributor.author | Chun-Yu Chiang | en |
| dc.contributor.author | 姜俊宇 | zh_TW |
| dc.date.accessioned | 2021-06-15T05:42:29Z | - |
| dc.date.available | 2013-08-20 | |
| dc.date.copyright | 2010-08-20 | |
| dc.date.issued | 2010 | |
| dc.date.submitted | 2010-08-20 | |
| dc.identifier.citation | [1] K. B. Hardin, J. T. Fessler, and D. R. Bush, “Spread Spectrum Clock Generation for the Reduction of Radiated Emissions,” in Proc. IEEE Int. Symp. Electromagnetic Compatibility, 1994, pp. 227-231.
[2] H. S. Li, Y. C. Cheng, and D. Puar, “Dual-Loop Spread-Spectrum Clock Generator,” in Proc. IEEE Int. Solid-State Circuit Conf., Feb. 1999, pp. 184-185. [3] M. Aoyama et al., “3Gbps, 5000ppm Spread Spectrum SerDes PHY with frequency tracking Phase Interpolators for Serial ATA,” in Proc. VLSI Circuits Symp., Jun. 2003, pp. 107-110. [4] M. Kokubo et al., “Spread-Spectrum Clock Generator for Serial ATA using Fractional PLL Controlled by ΔΣ Modulator with Level Shifter,” in Proc. IEEE Int. Solid-State Circuit Conf., Feb. 2005, pp. 160-161. [5] H. R. Lee, O. Kim, G. Ahn, and D. K. Jeong, “A Low Jitter 5000ppm Spread Spectrum Clock Generator for Multi-channel SATA Transceiver in 0.18μm CMOS,” in Proc. IEEE Int. Solid-State Circuit Conf., Feb. 2005, pp. 162-163. [6] R. E. Best, “Phase-Locked Loops,” 5th Ed., McGraw-Hill, 2003. [7] W. F. Egan, “Phase-Lock Basics,” Wiley-Interscience, 1998. [8] B. Razavi, “Design of Analog CMOS Integrated Circuits,’ McGraw-Hill, 2001. [9] B. Razavi, “RF Microelectronics,” Prentice Hall, 2003. [10] M. H. Perrott, M. D. Trott, and C. G. Sodini, “A Modeling Approach for Σ-Δ Fractional-N Frequency Synthesizers Allowing Straightforward Noise Analysis,” IEEE J. of Solid-State Circuits, vol. 37, pp. 839-849, Aug. 2002. [11] T. Yamawaki et al., “A 2.7-V GSM RF Transceiver IC,” IEEE J. Solid-State Circuits, vol. 32, pp. 2089-2096, Dec. 1997. [12] B. Razavi, “The Role of PLLs in Future Wireline Transmitters,” IEEE Trans. Circuits Syst. I, vol. 56, pp. 1786-1793, Aug. 2009. [13] Remco C. H. van de Beek et al., “A 2.5-10-GHz Clock Multiplier Unit With 0.22-ps RMS Jitter in Standard 0.18-μm CMOS,” IEEE J. Solid-State Circuits, vol. 39, pp. 1862-1872, April. 2004. [14] M. H. Perrott, “Fast and Accurate Behavioral Simulation of Fractional-N Frequency Synthesizers and other PLL/DLL Circuits,” in Proc. IEEE 39th Annu. Design Automation Conf., 2002, pp. 498-503. [15] S. Kim, K. Lee, Y. Moon, D.-K. Jeong, and H. K. Lim, “A 960-Mb/s/pin Interface for Skew-Tolerant Bus Using Low Jitter PLL,” IEEE J. Solid-State Circuits, vol. 32, pp. 691-700, May 1997. [16] J. T. Wu, H. D. Chang, P. F. Chen, “A 2V 100MHz CMOS Vector Modulator,” in Proc. IEEE Int. Solid-State Circuit Conf., Feb. 1997, pp. 80-81. [17] J. M. Hsu, “A 0.18-um CMOS Offset-PLL Upconversion Modulation Loop IC for DCS 1800 Transmitter,” IEEE J. Solid-State Circuits, vol. 38, pp. 603-613, April. 2003. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/46869 | - |
| dc.description.abstract | 在現今可攜式行動裝置被廣泛應用之下，為了達到高速的資料傳輸速度，個人電腦與外部儲存元件之間的高速介面變的更為重要。當資料在高速傳遞時，系統將遭受由高頻時脈所產生的電磁干擾。這種存在於電子產品中的非理想效應會造成嚴重的問題而必須被處理。SATA一種最具未來性的技術之ㄧ，並可提供高達6Gp/s的大頻寬。在SATA規範中，藉由展頻時脈技術來分散主要載波能量以達到降低電磁干擾的目的。
此論文提出一個以偏移式鎖相迴路為基礎，應用於SATA III的展頻時脈產生器。在此架構中，利用直接數位頻率合成器產生一個低頻的展頻時脈，並將此訊號藉由單邊帶混頻器升頻以產生一個高頻的參考調變輸入訊號。當達到鎖定狀態時，偏移式鎖相迴路將會產生所需的展頻時脈輸出。所設計的展頻時脈產生器製作使用標準0.11-μm互補金氧半導體邏輯製程且晶片面積為1.071 x 0.945 mm2，在1伏特電壓源供應下，功率消耗為15.22 mW。 | zh_TW |
| dc.description.abstract | As portable devices are widely used nowadays, the high-speed interfaces between the personal computer and the external storage devices are becoming critical in order to achieve high data transmission rate. When operating at high data rate, the systems often suffer from the electromagnetic interference (EMI) which is caused by the high-frequency clock. This non-ideal effect in electronic products is a serious issue which must be dealt with. Serial AT Attachment (SATA) is one of the most promising technologies providing large bandwidth up to 6 Gb/s. SATA specification defines an EMI reduction method using spread-spectrum clocking (SSC) to reduce the peak EMI emission by spreading the carrier frequency.
A spread spectrum clock generator (SSCG) based on an offset phase-locked loop (OPLL) for the Serial AT Attachment 3 (SATA III) is presented in this thesis. In the proposed architecture, a low-frequency spread spectrum signal is synthesized by a direct digital frequency synthesizer (DDFS) and mixed with a high frequency signal to produce a higher modulated reference source. The OPLL is employed to lock its output with the modulated reference to generate the desired spread spectrum clock. This SSCG is fabricated in a 0.11-μm CMOS technology and its area is 1.071 x 0.945 mm2. It draws 15.22 mW from a 1 V supply. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-15T05:42:29Z (GMT). No. of bitstreams: 1 ntu-99-R95943122-1.pdf: 4962608 bytes, checksum: fbf62e24e8322ba2278a92f2a5417fd3 (MD5) Previous issue date: 2010 | en |
| dc.description.tableofcontents | Table of Contents
Table of Contents I List of Figures V List of Tables IX Chapter 1 Introduction 1 1.1 Motivation and Research Goals 1 1.2 Thesis Overview 2 Chapter 2 Basic Concepts of Phase-Locked Loops 3 2.1 Introduction 3 2.2 Phase-Locked Loops 3 2.2.1 Simple PLL Topology 5 2.2.2 Linear Model of Simple PLL 6 2.2.3 Charge-Pump PLL 8 2.2.4 Linear Model of Charge-Pump PLL 10 2.3 Dual-Loop Architectures 13 2.4 Effect of Various Noise Sources in Phase-Locked Loops 15 Chapter 3 An OPLL-Based Spread Spectrum Clock Generator for SATA III 19 3.1 Introduction 19 3.2 Spread Spectrum Fundamentals 19 3.2.1 Modulation Profiles 19 3.2.2 Spread Spectrum Modes 21 3.2.3 Spread Spectrum Methods 23 3.3 Architectures of OPLL-Based SSCG 24 3.3.1 Offset-Phase Locked Loop (OPLL) 24 3.3.2 The Architecture of the Proposed SSCG 25 3.3.3 In-Band Noise Reduction 27 3.4 Behavioral Simulation 28 3.4.1 Bandwidth Selection 28 3.4.2 Comparison with Σ-Δ Frequency Synthesizer 31 3.4.3 Non-Ideality of SSB Mixer 34 Chapter 4 Circuit Implementation 37 4.1 Introduction 37 4.2 Architecture 37 4.3 Phase Frequency Detector 38 4.4 Charge Pump 40 4.5 Loop Filter 42 4.6 Single Side Band Mixer 45 4.7 Frequency Divider 45 4.8 Voltage-Controlled Oscillator 47 4.9 Transistor-Level Simulation 48 4.10 Layout and Floor Plan 50 Chapter 5 Test and Experimental Results 51 5.1 Introduction 51 5.2 Test Strategy 51 5.2.1 Test Setup 51 5.2.2 Print Circuit Board Design 52 5.3 Chip Die Photo 53 5.4 Experimental Results 53 Chapter 6 Conclusions 57 6.1 Conclusions 57 Bibliography 59 | |
| dc.language.iso | en | |
| dc.subject | 鎖相迴路 | zh_TW |
| dc.subject | 展頻 | zh_TW |
| dc.subject | 時脈產生器 | zh_TW |
| dc.subject | OPLL | en |
| dc.subject | SATA | en |
| dc.subject | SSCG | en |
| dc.title | 以偏移式鎖相迴路為基礎應用於SATA III之展頻時脈產生器 | zh_TW |
| dc.title | An OPLL-Based Spread Spectrum Clock Generator for SATA III | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 98-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 鄭國興,陳巍仁,黃柏鈞 | |
| dc.subject.keyword | 展頻,時脈產生器,鎖相迴路, | zh_TW |
| dc.subject.keyword | OPLL,SATA,SSCG, | en |
| dc.relation.page | 60 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2010-08-20 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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