7GHz,90ps,骨牌邏輯高速加法器及其測試架構

Abstract

在需要處理大量資訊的時代裡，高速的計算機一直是人們追求的目標，而其運算核心即是一個加法器，加法器在計算機中扮演著最基本且影響甚重的角色，其速度幾乎即決定了整體系統的效能。目前Intel已經開發出其專屬之稀疏樹前綴式加法器，且使用65nm製程將其32位元處理速度提升至6.4GHz。 本篇論文針對90nm製程，提出適合先進製程的改良式前綴式加法器，使資料運算更為同步。並使用動態骨牌邏輯實現以提升速度以及利用基板偏壓技術降低其消耗功率。此加法器在2009年3月已使用UMC 90nm製造而成，操作頻率為7GHz，運算延遲為90ps，消耗功率為31mW。 本篇論文亦提出了一精準的量測架構，能準確的量測加法器的運算延遲，其中包含了一個鎖相迴路(PLL)及一個延遲鎖相迴路(DLL)，鎖相迴路(PLL)為整個系統之時脈產生器，輸出訊號為7GHz之週期訊號，延遲鎖相迴路(DLL)被使用在輸入及輸出之間，操作頻率為7GHz，且在每個周期中包含了10個相位，藉由不同相位取得正確的輸出訊號，精確的量測其運算延遲。

With the growth of demand for high-speed and low power processors, it is essential to improve the performance of adders as it is one of the most critical parts of the processors. Some adder architectures are proposed to enhance the speed and power consumption, such as sparse tree of Intel. Intel also sped up the 32-bit adder to 6.4GHz in 65nm technology. In this thesis, we propose a 32bit modified prefix tree adder which consumes only four complex domino logic stages. It is applied to the characteristic of the Domino logic and deep submicron meter CMOS technology, decreasing gate loading but increasing wire loading. In addition, a well arranged and balanced interconnect route is implemented to reduce 70% cross-coupled capacitances. A test chip was fabricated in UMC 90-nm 1.2-V CMOS technology in March 2009, which is operated at 7GHz and with 90ps latency. The total chip area is 430um × 110um. And by substrate bias, we save power consumption up to 36.5% that caused by leakage current. In this thesis, we also propose a new efficient and precise circuit for testing, including a Phase-Lock-Loop (PLL) and a Delay-Lock-Loop (DLL). PLL is locked at 7GHz as the system clock. There are ten phases in one cycle of the DLL, which is operated at 7GHz. Because DLL is used between inputs and outputs of adder, we can measure the latency precisely by sampling the outputs with different phases.