低功率連續漸進式及管線式類比數位轉換器之設計與應用

Abstract

As the rapid growth on the development of the wireless communication system, the requirement for the ADC that connect the digital and analog circuits becomes stricter and stricter. In this thesis, two kinds of ADCs are implemented that contain power-saving techniques. In Chapter 3 of this thesis, a low power SAR ADC is presented which uses the advantage of the fully differential structure to decrease the requirement of capacitors, that makes the chip area smaller while get the same resolution as the traditional circuit. The chip is fabricated by TSMC 0.35um 2P4M CMOS technology and the measurement results will be shown. In Chapter 4, a pipelined ADC is introduced which uses opamp current reuse technique to decrease the power dissipation without summing node reset problem. As a result, we can get the advantage of pipelined ADC that has high operation speed without massive power consumption.