具有隔絕寬頻電源雜訊抑制效果之新型電磁能隙結構電源層：其模型與在射頻系統單晶片封裝之應用

Abstract

一種新型的電磁能係結構(Electromagnetic Bandgap Structure)電源層利用多連通柱的接地平面缺陷晶格(Multiple Via Ground Surface Perturbation Lattice)已被提出。此種電磁能係結構電源層提供寬頻的濾波效果用來抑制電源封裝系統中的接地彈跳雜訊(Simultaneous Switching Noise)耦合之傳遞。此種新型的電磁能係結構電源層是利用多連通柱的接地平面缺陷晶格與共平面式電磁能係結構電源層所組成。多連通柱的接地平面缺陷晶格是為週期性排列之金屬片以多根連通柱連接到共平面式電磁能係結構電源層之接地層，達到有效增加共平面式電磁能係結構電源層的效果。此電磁能係結構電源層能夠在不加額外元件下在提供140%比例頻寬。針對此結構，一個一維的等效電路也被提出用來快速預測其頻帶。此一維等效電路的有效性已由實驗與模擬做驗證，並用來建立參數設計曲線。為了研究電磁能係結構在混合信號系統的可行性，一個C 頻帶的低雜訊放大器已被設計用來作為一個研究案例。在模擬與量測中，此電磁能係結構電源層已被驗證在提供低雜訊放大器偏壓時能有效阻隔接地彈跳雜訊對放大器信號品質的干擾。在低雜訊放大器的輸出頻譜內約50%的雜訊干擾可以被抑制。

A novel EBG power/ground planes using LPC-EBG with multiple via ground surface perturbation lattice (MV-GSPL) is proposed. The proposed structure is used to provide superior stopband to suppress the simultaneous switching noise (SSN) coupling within typical power/ground planes. The MV-GSPL is periodically distributed metal patches shorting to the continuous ground plane and can be embedded in a coplanar type EBG structure to enhance its stopband. This structure is able to provide almost 140 fractional bandwidth without any additional component in a compact unit cell area. An efficient 1-D analysis model is also proposed. The 1-D model is able to consider the via effect of MV-GSPL on the stopband. In the application aspect, a test C-band low noise amplifier (LNA) fabricated by the TSMC 0.18um 1P6M process is packaged on the LPC-EBG with MV-GSPL substrate for noise immunity test. Both the chip-package co-simulation and experimental results show excellent power noise isolation capability of the RF package for the C-band LNA. The proposed EBG structure is confirmed possessing up to 50 % spurious noise reduction in output spectrum of the LNA.